Abstract: A method for identification of memory assignment conflicts in the assignment of memory location addresses to a set of buffers. Programs run in embedded processors using buffers in a fixed storage space need to be mapped to addresses which do not overlap or create conflicts. The process of assigning start and end addresses for buffers can be tedious and error prone if performed without automation. The present invention presents a tool that automates the task of mapping the memory buffers and heaps to physical space. The tool utilizes a memory buffer allocation table created by the programer. The table designates the locations, sizes and overlays of all the buffers and heaps. The tool checks the validity of the memory map specified. If it is found to be invalid, the user is notified of the error. Otherwise, a memory table is created which will serve as “hooks” for runtime buffer manipulation.

Abstract: A semiconductor package comprising a die adjacent a lead frame die pad, said lead frame die pad adapted to dissipate heat from the die. The package further comprises a thermally-conductive material abutting the die and a heatsink abutting the thermally-conductive material, said heatsink facing a direction opposite from the lead frame die pad.

Abstract: A method and system for performing spatial temporal multiplexing using a multi-threshold mask. A mask generator (404) outputs a threshold value for each pixel of a display. The mask generator typically creates a blue noise mask for a given pixel array that is replicated over the face of the entire display. The blue noise mask generator (404) typically is implemented as a memory lookup table. An index generator (402) provides an offset into the memory lookup table that allows the table to be shifted from time to time. The output of the blue noise mask generator (404), which may be the threshold value itself or a signal representing which threshold is being used, is an input to a selective inverter (406). The selective inverter (406) provides the option of inverting the blue noise mask. To reduce artifacts, the mask is periodically shifted and/or inverted. The value from the mask generator (404), whether inverted or not, is compared to the LSBs of the input data word to yield the fractional bit values.

Abstract: A circuit (48) and method, which can be used in a mass data storage device, controls adaptation asymmetry of coefficients of an FIR filter (20) using an accumulator (52) or accumulating correlation results between unequalized FIR filter input data samples and FIR filter output equalized error samples. A circuit (52) generates coefficient increment and decrement requests from the accumulated correlation results. A circuit (120,102?,122) updates the coefficients within a symmetric coefficient pair on the basis of the increment and decrement requests only if a predetermined nonzero coefficient magnitude difference between the coefficient pair would not be exceeded by the update.

Abstract: Gain and phase imbalance is estimated by using an IQ-swapped spreading sequence in addition to a regular spread pilot signal. The IQ-swapped spreading sequence is the spreading sequence whose real and imaginary components are the imaginary and real components of the regular spreading sequence. The gain imbalance can be estimated by a function of the difference between the real component of a regular despread pilot signal and the imaginary component of the IQ-swapped pilot signal. In a similar fashion, the phase imbalance is estimated by a function of the difference between the imaginary component of a regular despread pilot signal and the real component of the IQ-swapped despread pilot signal. A controller such as a DSP (102) uses the gain and phase imbalance estimates to control a gain and phase correction circuit (104). In one embodiment, the correction circuit (104) includes a plurality of multipliers (202–212) and a ROM look-up-table (202) in order to perform the imbalance correction.

Abstract: The present invention provides a post-channel estimate phase corrector for use with a multiple-input, multiple-output (MIMO) receiver employing M receive antennas, M being at least two. In one embodiment, the post-channel estimate phase corrector includes a pilot sequence coordinator configured to receive a pattern of pilot sequences from the M receive antennas during data symbol time periods. The post-channel estimate phase corrector also includes a phase calculator coupled to the pilot sequence coordinator and configured to calculate phase corrections for individual channel estimates based on the pattern of pilot sequences.

Abstract: A system and method for improving bit-loading in discrete multitone (DMT)-based digital subscriber line (DSL) modems. In one embodiment, the system includes: (1) a model generator configured to generate a model containing a calculated total bit loading for an assumed gross coding gain and estimated total bit loadings for a other plurality of assumed gross coding gains and (2) a bit loader associated with the model generator and configured to load bits in accordance with the model.

Abstract: The present invention provides, in one aspect, a method of designing an integrated circuit 500. In this particular aspect, the method comprises reducing soft error risk in an integrated circuit 500 by locating a structure 526, 528 relative to a node 516 of the integrated circuit 500 to reduce a linear energy transfer associated with a sub-atomic particle 530, 532 into the node 516, such that the linear energy transfer does not exceed a threshold value associated with the integrated circuit 500.

Abstract: A clock synthesis circuit) including a phase-locked loop and one or more frequency synthesis circuits is disclosed. The phase-locked loop includes a voltage-controlled oscillator (VCO) having a sequence differential stages o produce equally spaced clock phases. The frequency synthesis circuit includes a sequence of adder-and-register units that select one of the VCO clock phases. An output multiplexer receives each of the selected clock phases, and selects among these clock phases in sequence; the output of the multiplexer is applied to a first toggle flip-flop that changes state in response to rising edge transitions at the output of the multiplexer. A second toggle flip-flop is clocked by the output of the first toggle flip-flop, itself toggling in response to rising edge transitions at the output of the first toggle flip-flop. One or more additional flip-flops can be similarly connected in sequence.

Abstract: The present invention provides, in one aspect, a method of imaging a microelectronics device 100. The method comprises cleaning, when contaminants are preset, a sample of a microelectronics device 100 to be imaged with a first solution comprising hydrofluoric acid, an inorganic acid and water, exposing the sample to a second solution comprising hydrofluoric acid, an inorganic acid and an organic acid, wherein the second solution forms a contrast between different regions within the sample, and producing an image of the contrasted sample.

Abstract: The present invention provides a single torsional hinge device, such as a mirror, adapted for use as a pivoting mirror and preferably a pivoting mirror oscillating at a resonant frequency about the single hinge. The single torsional hinge mirror reduces or substantially eliminates stresses on the torsional hinge mirrors caused by mismatched mounting levels of the support structure and/or differences of the coefficient and thermal expansion of materials in the mirror and support structures. The mirror may include a single layer of silicon having a reflective surface or may be a multilayered mirror wherein silicon is used for the torsional hinges and support and silicon or other materials may be used as the reflecting surface.

Abstract: A digital amplifier includes a noise shaper and a dither generator arranged to introduce noise to the shaper. The generator uses a seed value derived from a state variable of the shaper.

Abstract: An oscillator circuit comprises a plurality of ring oscillators wherein each ring oscillator produces an oscillatory output signal. The ring oscillators are cross-coupled such that each ring oscillator drives only one other ring oscillator. In at least one embodiment, the oscillator circuit comprises four, three-stage ring oscillators. As such, each ring oscillator comprising three cells (e.g., inverters or delay elements). Further, in this embodiment, the oscillator circuit produces a four phase clock comprising the oscillatory output signals from each of the four ring oscillators.

Abstract: A programmable voltage regulator configurable for reverse blocking and double power density is disclosed herein. The programmable voltage regulator includes an error amplifier that couples to receive a reference voltage. A first NMOS pass transistor connects between an auxiliary voltage input node and the output terminal of the voltage regulator, wherein the first NMOS pass transistor is biased by the output of the error amplifier. Connected between the source of the first NMOS pass transistor and the second input of the error amplifier, a feedback network provides feedback for the voltage regulator. A second NMOS pass transistor connects between the first power supply and the auxiliary voltage input node. Furthermore, an independent node control circuit biases the second NMOS pass transistor such that in a first mode of operation, a first control signal input is operable to receive a signal for controlling the second NMOS pass transistor during reverse battery condition.

Abstract: A wireless communications base station (10) having a digital bit modulation function (72) is disclosed. The bit modulation function (72) may be realized by a software routine executable by a programmable device such as a digital signal processor (40), or alternatively by dedicated logic circuitry. The bit modulation function (72) receives a datastream corresponding to the payload, and a scrambling code, each of which include an in-phase component and a quadrature component. The bit modulation function (72) corresponds to a split adder (94) that performs a Gray Code addition of corresponding bits of the in-phase and quadrature data components with corresponding bits of the in-phase and quadrature scrambling code components. The result is a combined in-phase bit and a combined quadrature bit for each bit position in the datastream. The Gray Code addition takes the place of a complex multiplication, thus saving significant processing capacity or reducing circuit complexity.

Abstract: An imaging architecture is provided employing CMOS imaging sensors. The imaging architecture utilizes time domain sampling techniques to extract image data from a photodiode (PD) pixel array. The CMOS imaging architecture associates time index values with firing of CMOS imaging sensors in response to a capture of an image. The time index values correspond to the brightness of the illumination received by the CMOS imaging sensor. The time index value associated with the firing of the CMOS imaging sensor can be stored and employed in reconstruction of the image. The imaging architecture includes systems and methods for reading and compressing imaging data extracted from the PD pixel array.

Abstract: An embodiment of the invention is an integrated circuit 2 having antenna proximity lines 3 coupled to the semiconductor substrate 5. Another embodiment of the invention is a method of manufacturing an integrated circuit 2 having antenna proximity lines 3 coupled to the semiconductor substrate 5.

Abstract: A new heat sink apparatus and method that simplify the assembly of the heat sink and thermal stud. The new heat sink assembly uses a spring retainer that, in most cases, can use existing socket mounting screws. A spring clip (202) presses a thermal stud (204) against the back of an electrical device package (206). The present invention is especially useful for attaching a spatial light modulator to a printed circuit board (106) since it provides a simple, reliable heat sink without blocking the light path to and from the device. The preceding abstract is submitted with the understanding that it only will be used to assist in determining, from a cursory inspection, the nature and gist of the technical disclosure as described in 37 C.F.R. § 1.72(b). In no case should this abstract be used for interpreting the scope of any patent claims.

Abstract: A method and an apparatus for uniform electroless plating of layers onto exposed metallizations in integrated circuits such as bond pads. The apparatus provides means for holding a plurality of wafers, and rotating each wafer at constant speed and synchronous within the plurality. Immersed in a plating solution flowing in substantially laminar motion and at constant speed, the method creates periodic superposition of directions and speeds of the motion of the wafers and the motion of the plating solution. The invention creates periodically changing wafer portions where the directions and speeds are additive and where the directions and speeds are opposed and subtractive. Consequently, highly uniformly layers are electrolessly plated onto the exposed metallizations of bond pads. If the plated layers are bondable metals, the process transforms otherwise unbondable pad metallization into bondable pads.

Abstract: Method for assembling a semiconductor device having fatigue-resistant interconnection fillet provides a semiconductor chip with at least one solder bump comprising an alloy of tin and lead with a melting temperature higher than the solder paste used. Further, a solder paste (preferably binary) is provided, which comprises tin and about 2.5 weight percent silver, and has a melting temperature of about 221° C. The solder bump is brought in contact with the solder paste, the bump is partially immersed in the paste, and thermal energy is supplied to reflow the solder paste at about 235° C. The amount of energy and time after the reflow of the paste is controlled so that the molten paste dissolves a pre-determined amount of the solder bump (lead and tin) to form a ternary alloy of about eutectic composition (about 1.62 weight % Ag, 36.95 weight % Pb, 61.43 weight % Sn) without melting the solder bump.