Abstract: A method of manufacturing a semiconductor device includes the steps of providing a semiconductor substrate (102), forming a dielectric layer (104) over the semiconductor substrate (102), and etching a trench structure (106) or a via structure (106) in the dielectric layer (104) to expose a portion of a surface of the semiconductor substrate (102). The method also includes the steps of treating a surface (104a) of the dielectric layer (104) with an adhesion solution, such as a reactive plasma including hydrogen, and forming a diffusion barrier layer (110) over the dielectric layer (104). Moreover, the adhesion solution chemically interacts with the surface (104a) of the dielectric layer (104) and enhances or increases adhesion between dielectric layer (104) and diffusion barrier layer (110).

Abstract: A small vocabulary speech recognizer suitable for implementation on a 16-bit fixed-point DSP is described. The input speech xt is sampled at analog-to-digital (A/D) converter 11 and the digital samples are applied to MFCC (Mel-scaled cepstrum coefficients) front end processing 13. For robustness to background noises, PMC (parallel model combination) 15 is integrated. The MFCC and Gaussian mean vectors are applied to PMC 15. The MFCC and PMC provide speech features extracted in noise and this is used to modify the HMMs. The noise adapted HMMs excluding mean vectors are applied to the search procedure to recognize the grammar. A method of computing MFCC comprises the steps of: performing dynamic Q-point computation for the preemphasis, Hamming Window, FFT, complex FFT to power spectrum and Mel scale power spectrum into filter bank steps, a log filter bank step and after the log filter bank step performing fixed Q-point computation. A polynomial fit is used to compute log2 in the log filter bank step.

Abstract: The present invention provides a system for limiting degradation of a first semiconductor structure (304) caused by an electric field (314), generated from within the semiconductor substrate (302) by high voltage on a second semiconductor structure (310). A semiconductor device (300) is adapted to reduce the effective magnitude of the field—as realized at structure 304—to some fractional component (320), or to render the angle (322)—at which the field approaches the first structure through a first substrate region (306)—acute. Certain embodiments of the present invention provide for: lateral recession of the first semiconductor structure to abut an isolation structure (312), which is disposed between the second semiconductor structure and the first substrate region; lateral recession of the first semiconductor structure from the isolation structure, so as to form a moat therebetween; and a counter-doped region (316) within the first substrate region.

Abstract: A method for forming a SOI structure in which porous silicon is sealed and an epitaxial layer is grown thereover, followed by implantation of oxygen and annealing.

Abstract: Spread spectrum receiver with correlating coprocessor having common datapath for received signal correlations and code cross-correlations for efficient interference cancellation methods.

Abstract: A high output current wideband output stage/buffer amplifier that has reduced quiescent current requirements. The output stage/buffer amplifier includes a diamond follower circuit having a pair of complementary output load-driving bipolar junction transistors (BJTs), a pair of pre-driver BJTs, and a plurality of current boost BJTs. As the base current of one of the driver transistors starts to increase in response to an increasing load current, the current through a corresponding pre-driver transistor decreases, thereby increasing the collector current of a corresponding boost transistor. The increased collector current of the boost transistor is fed back to a current mirror, causing a concomitant increase in the base current of the driver transistor.

Abstract: A controller providing increased control with lesser final error for an actuator when there is a force accelerating the actuator, such as at the end of travel during a retract operation. An extension of the integrator may be provided for implementing a second direction to integrate a final error. One embodiment of the invention may comprise a counter and an analog multiplexer controlling the attenuation of the command voltage.

Abstract: An interactive translation system (10) includes a front end (40), a back end (42), and a user interface (16). The front end (40) is operable to identify source elements (86) in a source file (24). The back end (42) is operable to generate a translation file having translation elements corresponding to translation of said identified source elements (86) and having an interface (16) for receiving inputs for modifying said translation.

Abstract: A wireless communication system. The system comprises transmitter circuitry (BST1), the transmitter circuitry comprising encoder circuitry (50) for transmitting a plurality of frames (FR). Each of the plurality of frames comprises a primary synchronization code (PCS) and a secondary synchronization code (SSC). The encoder circuitry comprises of circuitry (501) for providing the primary synchronization code in response to a first sequence (32). The encoder circuitry further comprises circuitry (502) for providing the secondary synchronization code in response to a second sequence (54) and a third sequence (56). The second sequence is selected from a plurality of sequences. Each of the plurality of sequences is orthogonal with respect to all other sequences in the plurality of sequences. The third sequence comprises a subset of bits from the first sequence.

Abstract: An integrated circuit (IC) package 100 comprises an IC 102 and leads 104 coupled to the IC. Each lead has a first end 106 configured to be coupled to the integrated circuit and a second end 108 configured to pass through one of a plurality of mounting holes 110 extending through a mounting board 112. The leads comprise at least one positioning lead 114 comprising a stop 118 being a continuous part of the positioning lead and having a lateral dimension 120 greater than a diameter 122 of a first hole 124 of the plurality of mounting holes. The leads further comprise at least one non-positioning lead 116 having a continuous uniformly shaped body 130 with a lateral dimension 132 less than a diameter 134 of a second hole 136 of the plurality of mounting holes. The stop limits an extension of the non-positioning lead through the second hole.

Abstract: A method of manufacturing an etch stop layer 18, 20, 21 on a semiconductor wafer 2 and the etch stop layer 18, 20, 21 produced by the method. The method includes depositing a dielectric layer 18, 20, 21 and applying a plasma treatment to the semiconductor wafer 2. Also, an etch stop layer 18, 20, 21 on a semiconductor wafer 2 having a modified surface and an amine deficient bulk.

Abstract: The present invention provides a method for manufacturing a semiconductor device having an alignment feature. The method for manufacturing the semiconductor device, among other steps, may include implanting an n-type dopant into a substrate thereby forming an implanted region and an unimplanted region in the substrate. The method may further include oxidizing the substrate using a wet oxidation process, the wet oxidation process and n-type dopant causing a ratio of oxidation of the implanted region to the unimplanted region to be 2:1 or greater, and then removing the oxidized portions of the substrate thereby leaving an alignment feature proximate the implanted region.

Abstract: A first-order signal generator (135). The generator comprises a shift register (210?) having a number N of bit positions. Each bit position is operable to store a binary value, the shift register operable to shift the binary value at each of the bit positions. The generator also comprises circuitry for tapping selected ones of the bit positions and circuitry for applying a function (220?) to each binary value in the selected ones of the bit positions to provide a function output. The generator also comprises circuitry for coupling the function output as an input to one of the bit positions.

Abstract: An iterative forward error control code (FECC) decoder (28; 28?) is disclosed. The decoder (28; 28?) operates by adjusting probability values for codeword bits at a selected iteration in the decoding sequence. According to one disclosed embodiment, those probability values that are above a certain threshold value prior to one of the last decoding iterations are adjusted to a full reliability value. According to other disclosed embodiments, a linear or non-linear adjustment function is applied. The decoder may be a turbo decoder, a Low Density Parity Check (LDPC) decoder, or a decoder for any FECC code for which iterative decoding is appropriate.

Abstract: A cache system comprises a plurality of cache banks, a translation look-aside buffer (TLB), and a scheduler. The TLB is used to translate a virtual address (VA) to a physical address (PA). The scheduler, before the VA has been completely translated to the PA, uses a subset of the VA's bits to schedule access to the plurality of cache banks.

Abstract: A wireless transmitter (TX1). The transmitter comprises circuitry for providing a plurality of control bits (CONTROL) and circuitry for providing a plurality of user bits (USER). The transmitter further comprises circuitry (16) for modulating the plurality of control bits and the plurality of user bits into a stream of complex symbols and circuitry (18) for converting the stream of complex symbols into a parallel plurality of complex symbol streams. The transmitter further comprises circuitry (20) for performing an inverse fast Fourier transform on the parallel plurality of complex symbol streams to form a parallel plurality of OFDM symbols and circuitry (22) for converting the parallel plurality of OFDM symbols into a serial stream of OFDM symbols. The serial stream consists of an integer N+1 OFDM symbols. Each OFDM symbol in the serial stream of OFDM symbols comprises a plurality of data points. Finally, selected OFDM symbols (SF1.

Abstract: A digital device 310 with a plurality of collocated wireless networks encounters inter-network interference if the collocated wireless networks operate in a common operating frequency. A coordinator unit 510, coupled to the plurality of wireless networks, provides a transmission reservation system wherein a wireless network with a need to transmit can request and receive a reservation for time to transmit. The coordinator unit 510 provides a way to schedule transmissions from the plurality of wireless networks and to reduce the probability of collisions.

Abstract: The present invention provides, in one embodiment, a method of fabricating a semiconductor device (100). In one embodiment, the method includes growing an oxide layer 120 from a substrate 104, 106 over a first dopant region 122 and a second dopant region 128, implanting a first dopant through the oxide layer 120, into the substrate 104 in the first dopant region 122, and adjacent a gate structure 114, and substantially removing the oxide layer 120 from the substrate within the second dopant region 128. Subsequent to the removal of the oxide layer 120 in the second dopant region 128, a second dopant that is opposite in type to the first dopant is implanted into the substrate 106 and within the second dopant region 128 and adjacent a gate structure 114.

Abstract: Narrowband interference can seriously degrade the overall performance of a communications network without significantly damaging a large percentage of the communications network's transmissions. In a single tone communications network, narrowband interference can reduce the overall signal-to-noise ratio to a level such that a receiver can no longer accurately decode the received transmission. However, the receiver's filters and equalizers often can filter out the effects of the narrowband interference and the receiver can accurately decode the received transmission if the receiver can restart the decoding at the point when the narrowband interference began interfering with the transmission. A technique using sequential decoding with backtracking and adaptive equalization permits the receiver to adapt to the presence of the narrowband interference and backtrack the decoding to a point prior to the interference.

Abstract: Methods are disclosed for semiconductor device fabrication in which dopants are selectively implanted into transistor gate structures to counteract or compensate for dopant depletion during subsequent fabrication processing. A patterned implant mask is formed over a semiconductor device, which exposes at least a portion of the gate structure and covers the remaining upper surfaces of the device. Thereafter, dopants are selectively implanted into the exposed gate structure.