Abstract: When wireless communications systems are operating in the same general area, collisions between their transmissions are bound to occur. The collisions reduce the performance in the networks. In some wireless communications systems that use a fixed or prespecified transmission frequency pattern, a look-ahead technique that investigates the quality of the communications channel at the upcoming transmission frequencies can be used to allow or disallow transmissions. Additionally, a maximum length of a transmission can be determined based on the quality of the transmission frequency. Finally, if the communications system is controlled by a centralized controller, moving the controller away from sources of interference will often improve performance.

Abstract: The present invention includes a plurality of FETs (211, 212, 213, 214, 215, 216, 217) including an operational amplifier with additional FETs (218, 219, 220,221) arranged as current mirrors, and a sense FET (101), and a current sensed at FET (101) is amplified, compared to a reference signal, the difference current derived from the amplified sense current and reference signal being amplified and provided at an output for use in control applications.

Abstract: An apparatus and method for using self-timing logic to make at least two accesses to a memory core in one clock cycle is disclosed. In one embodiment of the invention, a memory wrapper (28) incorporating self-timing logic (36) and a mux (32) is used to couple a single access memory core (30) to a memory interface unit (10). The memory interface unit (10) couples a central processing unit (12) to the memory wrapper (28). The self-timing architecture as applied to multi-access memory wrappers avoids the need for calibration. Moreover, the self-timing architecture provides for a full dissociation between the environment (what is clocked on the system clock) and the access to the core. A beneifical result of the invention is making access at the speed of the core while processing several access in one system clock cycle.

Abstract: An on-chip test mechanism for transceiver power amplifier and oscillator frequency for use with the transmitter portion of an integrated RF transceiver. The RF output from the power amplifier in the transmitter is input to a built-in dedicated analog comparator having a configurable threshold. The threshold is adjusted to a predetermined level at which crossings start to occur at the comparator output. The comparator outputs pulses only if the power amplifier output is above a minimum configurable level. The comparator output is input to a frequency divider whose frequency output is tested by a low cost external tester to determine the actual RF frequency thereby confirming generation of the correct oscillator frequency and that the amplitude of the signal at the output of the power amplifier is sufficiently high for the configurable threshold level to be exceeded, thereby determining the compliance of the output power with its defined specifications.

Abstract: The present invention covers circuits to achieve high data rate writing.

Abstract: System for providing a switched regulator with an adjustable operating frequency range. A preferred embodiment comprises a voltage supply and a load, a switch and filter block (SFB) (such as the SFB 510), a comparator (such as the comparator 520), and a fixed off time logic (FOTL) (such as the FOTL 525). The comparator compares an output voltage with a reference voltage. When the output voltage is equal to or exceeds the reference voltage, the comparator asserts a value on a signal line to the FOTL. The FOTL then shuts down the SFB for a specified period of time. During the off time, the output voltage decays. After the specified period of time expires, the SFB is turned back on and the output voltage can recharge. The duration of time that the SFB remains on is a function of the supply voltage, thus permitting an adjustable operating frequency.

Abstract: A high-speed signal level detector employs the high gain and high bandwidth of an inverter to perform a comparison. The high-speed signal level detector is capable of achieving the desired high-speed level detection without demanding the substantial power consumption required when using either the averaging technique or a high bandwidth op-amp type comparator.

Abstract: A phase detector in a delay locked loop circuit operates to determine the status of propagation of a first pulse of a reference clock signal (CKref) through a delay line (21). A first control signal (DOWN) is produced a in response to represent a first time at which the first pulse has progressed entirely through the delay line (21) and a later second time at which a next second pulse of the reference clock signal (CKref) arrives at a first input of the phase detector (24A). The delay of the delay line (21) is reduced in response to the first control signal (DOWN). A second control signal (UP) is produced in response to the status to represent a third time at which the second pulse of the reference clock signal (CKref) arrives at the first input of the phase detector (24A) and a later fourth time at which the first pulse of the reference clock signal (CKref) has progressed to the end of the delay line (21) and is used to increase the delay of the delay line (21).

Abstract: Disclosed are new methods and systems for achieving calibration in a pipelined ADC system. The methods and systems may be used to provide continuous digital background calibration in a pipelined ADC. Component mismatch error from each DAC in the pipeline is tabulated to provide an integral nonlinearity profile, which is subtracted from the ADC transfer characteristic.

Abstract: A compressor of a multiplier according to an embodiment of the present invention includes a first compressor, in which the first compressor includes a first plurality of inputs. The first compressor also includes a summation output, a first carry bit output; and a first plurality of transistor paths connecting each of the first plurality of inputs to the summation output. The compressor also includes a successive compressor, in which the successive compressor includes a second plurality of inputs and a plurality of successive transistor paths connecting at least one of the first plurality of inputs to the first carry bit output and connecting the first carry bit output to at least one of the second plurality of inputs. In one embodiment of the present invention, a first compressor critical transistor stage path level within the first compressor is less than seven and a successive compressor critical transistor stage path level within the successive compressor is less than eight.

Abstract: A magnetic drive for providing pivotal motion to a functional surface, such as a mirror. The magnetic drive may be used to drive any torsional hinged device, but is particularly suitable for driving a torsional hinged mirror. According to a first embodiment, a dual axis functional surface uses a first pair of torsional hinges to provide primary movement to the functional surface and a second pair of torsional hinges provides movement orthogonal to the primary movement to allow positioning in two directions. The mass and movement of inertia of the functional surface is reduced by relocating permanent magnet sets to the axis of rotation. The reduced mass and movement of inertia results in a stiff robust hinge having a resonant frequency above about 120 Hz.

Abstract: The present invention provides a system for limiting energy levels across the output of a driver circuitry segment (100). The system provides an output structure (102) adapted to drive an output load (104). A transconductance component (106) is communicatively coupled to the output structure, and adapted to output a transconductance current that is proportional to the voltage across the output structure. A scaling component (108) is communicatively coupled to the output structure, and adapted to output a scaled current that is proportional, by some scaling factor, to the current through the output structure. A qualifying component (110) is communicatively coupled to the scaling component, and adapted to activate a trigger component (112) when the scaled current passes a first threshold. The trigger component is communicatively coupled to the qualifying component, the transconductance component, and the output structure.

Abstract: Solder contacts can be formed on the conductive sites of a substrate by placing preformed solder balls on the conductive sites and then reflowing the solder balls to bond the solder balls to the conductive sites. After formation of the solder contacts, solder flux can be applied to at least a portion of the solder contacts. The solder contacts can then be reflowed to substantially improve the adhesion of the solder contacts to the conductive sites and increase the shear strength of the solder contacts.

Abstract: The present invention pertains to formation of a transistor in a manner that mitigates parasitic capacitance, thereby facilitating, inter alia, enhanced switching speeds. More particularly, a sidewall spacer formed upon a semiconductor substrate adjacent a conductive gate structure includes a material having a low dielectric constant (low-k) to mitigate parasitic capacitance between the gate structure, the sidewall spacer and a conductive drain formed within the semiconductor substrate. The low-k sidewall spacer is encapsulated within a nitride material which is selective to etchants such that the spacer is not altered during subsequent processing. The spacer thus retains its shape and remains effective to guide dopants into desired locations within the substrate.

Abstract: The present invention relates to electro static discharge (ESD) protection circuitry. Multiple techniques are presented to adjust one or more ends of one or more fingers of an ESD protection device so that the ends of the fingers have a reduced initial trigger or breakdown voltage as compared to other portions of the fingers, and in particular to central portions of the fingers. In this manner, most, if not all, of the adjusted ends of the fingers are likely to trigger or fire before any of the respective fingers completely enter a snapback region and begin to conduct ESD current. Consequently, the ESD current is more likely to be distributed among all or substantially all of the plurality of fingers rather than be concentrated within one or merely a few fingers. As a result, potential harm to the ESD protection device (e.g., from current crowding) is mitigated and the effectiveness of the device is improved.

Abstract: A switching regulator having a current limit with adaptive cycle skipping. A buck type switching regulator circuit is provided, including an energy storage component, such as an inductor or capacitor, and a switch for controllably providing an input current to the energy storage component. A control unit controls the on time and the off time of the switch by providing cyclically recurring control pulses to the switch that cause the switch to be on during the pulses and off otherwise. A current monitor circuit monitors a current corresponding to the input current applied to the energy storage component during the periodic control pulses. An overcurrent signal generator generates an overcurrent signal pulse upon detection of the monitored current at a level above a predetermined level corresponding to an overcurrent condition.

Abstract: Bipolar transistors and methods for fabricating bipolar transistors are disclosed wherein an emitter-base dielectric stack is formed between emitter and base structures, comprising a carbide layer situated between first and second oxide layers. The carbide layer provides an etch stop for etching the overlying oxide layer, and the underlying oxide layer provides an etch stop for etching the carbide layer to form an emitter-base contact opening.

Abstract: A technique to attenuate even-order harmonics of an output stage of a multistage nested Miller compensation circuit. In one example embodiment, this is accomplished by using a low-bandwidth low-swing amplifier in the common mode feedback loop to improve the even-order harmonic performance in the signal path. The technique uses a separate multistage loop for the common mode feedback loop to attenuate the even-order harmonics. The common mode feedback loop is the fourth stage and uses the third stage of the nested Miller compensation circuit. The fourth stage of the common mode feedback loop includes a single harmonic and uses a low voltage supply to achieve lower power consumption by the common mode feedback loop.

Abstract: The present invention provides a collision avoidance manager for use with single-port memories. In one embodiment, the collision avoidance manager includes a memory structuring unit configured to provide a memory arrangement of the single-port memories having upper and lower memory banks arranged into half-memory portions. Additionally, the collision avoidance manager also includes a write memory alignment unit coupled to the memory structuring unit and configured to provide double-data writing to the memory arrangement based on memory collision avoidance. In a preferred embodiment, the collision avoidance manager also includes a read memory alignment unit coupled to the memory structuring unit and configured to provide double-data reading from the memory arrangement while maintaining the memory collision avoidance.

Abstract: A method of forming an integrated circuit transistor (50). The method provides a first semiconductor region (52) and forms (110) a gate structure (54x) in a fixed position relative to the first semiconductor region. The gate structure has a first sidewall and a second sidewall (59x). The method also forms at least a first layer (58x, 60x) adjacent the first sidewall and the second sidewall. The method also forms (120) at least one recess (62x) in the first semiconductor region and extending laterally outward from the gate structure. Additional steps in the method are first, oxidizing (130) the at least one recess such that an oxidized material is formed therein, second, stripping (140) at least a portion of the oxidized material, and third, forming (160) a second semiconductor region (66x) in the at least one recess.