Abstract: A system and method for a plunger assembly includes a tuning slug with a bore in the stem, a tuning screw rotatably disposed in the stem, and a coupling assembly to rotatably secure the tuning screw to the slug. The system and method may also include a locking assembly to secure the postion of the assembly.

Abstract: The present invention provides a semiconductor device (200), a method of manufacture therefor and an integrated circuit including the same. In one embodiment of the invention, the semiconductor device (200) includes a floating gate (230) located over a semiconductor substrate (210), wherein the floating gate (230) has a metal control gate (250) located thereover. The semiconductor device (200), in the same embodiment, further includes a dielectric layer (240) located between the floating gate 230 and the metal control gate (250), the dielectric layer (240) having a gettering material located therein.

Abstract: A method of tracing program counter activity in a data processor periodically transmits a program counter sync point including the current program counter address. Between sync points the program counter address is indicated by a program counter offset relative to the last program counter sync point. The program counter offset is sent as integral number of sections of a predetermined number of bits. Program counter sync points are transmitted often enough so that the program counter offset requires at most one less section than the program counter address.

Abstract: A saturating count counts received event signals up to a first predetermined number. An overflow counter counts overflows up to a second predetermined number. The counter indicates overflow when the overflow count is non-zero and saturates and stops counting at a maximum count when the overflow count reaches the second predetermined number. The counter can be read via a register read operation. The sum of the sum of the first predetermined number of bits and the second predetermined number of bits being an integral multiple of 8 bits.

Abstract: The present invention comprises a pair of circuits (171, 172) within the first stage (100) of an AC signal pre-amplifier. The present invention reduces the current mismatch at the base of the first stage transistors (141, 142, 143, 144) resulting in faster switching times by reducing input stage offset and, hence improving input dynamic range.

Abstract: A semiconductor integrated circuit comprises contact pads located over active components, which are positioned to minimize the distance for power delivery between a selected pad and one or more corresponding active components, to which the power is to be delivered. This minimum distance further enhances dissipation of thermal energy released by the active components. More specifically, a semiconductor integrated circuit comprises a laterally organized power transistor, an array of power supply contact pads distributed over the transistor, means for providing a distributed, predominantly vertical current flow from the contact pads to the transistor, and means for connecting a power source to each of the contact pads. Positioning the power supply contact pads directly over the active power transistor further saves precious silicon real estate area.

Abstract: A patterned plasma treatment may be provided on the chip and/or the substrate to enhance the distribution of underfill material between the chip and the substrate. The underfill material is typically dispensed after the chip is electrically connected to the substrate. The chip may be electrically connected to the substrate by an array of solder bumps, as one example. The underfill material is draw into a gap between the chip and the substrate by a capillary action. The patterned plasma-treated area formed on the chip and/or on the substrate may cause greater capillary force on the underfill material, as compared to non-plasma-treated areas. Such patterned plasma-treatment area may be designed and laid out to provide for more or better control of the underfill distribution between the chip and substrate while forming a chip package.

Abstract: A transfer request bus and transfer request bus node is described which is suitable for use in a data transfer controller processing multiple concurrent transfer requests despite the attendant collisions which result when conflicting transfer requests occur. Transfer requests are passed from an upstream transfer request node to downstream transfer request node and then to a transfer request controller with queue. At each node a local transfer request can also be inserted to be passed on to the transfer controller queue. Collisions at each transfer request node are resolved using a token passing scheme wherein a transfer request node possessing the token allows a local request to be inserted in preference to the upstream request.

Abstract: Methods are disclosed that fabricating semiconductor devices with high-k dielectric layers. The invention removes portions of deposited high-k dielectric layers not below gates and covers exposed portions (e.g., sidewalls) of high-k dielectric layers during fabrication with an encapsulation layer, which mitigates defects in the high-k dielectric layers and contamination of process tools. The encapsulation layer can also be employed as an etch stop layer and, at least partially, in comprising sidewall spacers. As a result, a semiconductor device can be fabricated with a substantially uniform equivalent oxide thickness.

Abstract: Methods are presented for fabricating transistor gate structures, wherein upper and lower metal suicides are formed above a gate dielectric. In one example, the lower silicide is formed by depositing a thin first silicon-containing material over the gate dielectric, which is implanted and then reacted with a first metal by annealing to form the lower silicide. A capping layer can be formed over the first metal prior to annealing, to prevent oxidation of the metal prior to silicidation, and a barrier layer can be formed over the lower silicide to prevent reaction with subsequently formed silicon material. In another example, the lower silicide is a multilayer silicide structure including a plurality of metal silicide sublayers.

Abstract: An all-digital frequency synthesizer architecture is built around a digitally controlled oscillator (DCO) that is tuned in response to a digital tuning word (OTW). In exemplary embodiments: (1) a gain characteristic (KDCO) of the digitally controlled oscillator can be determined by observing a digital control word before and after a known change (?fmax) in the oscillating frequency; and (2) a portion (TUNE_TF) of the tuning word can be dithered (1202), and the resultant dithered portion ( d k TF ) can then be applied to a control input of switchable devices within the digitally controlled oscillator.

Abstract: While fabricating a packaged semiconductor chip, a wire is bonded on a chip contact pad using a wire bonding machine. A bond head of the wire bonding machine is moved relative to the chip contact pad, thereby pulling a first length of the wire out of the wire bonding machine. Part of the wire passes through a space between a first outer edge of a first bearing race and a second outer edge of a second bearing race during the pulling of the first length. The wire is bonded on a lead. A first piezoelectric element is energized in the bond head, thereby causing it to expand and press against the first bearing race, which brakes the first bearing race and brakes the wire between the first and second races. The bond head is moved relative to the lead during the braking and severs the wire proximate to the lead.

Abstract: A method of tracing data processor activity includes trace data markers indicating initiation and termination of at least one trace function at a specified program counter address and emulation pause related markers indicating initiation and termination of an emulation halt state at a specified program counter. Each emulation pause related marker includes a conflict bit indicating the presence or absence of a simultaneous trace data marker having a different program counter address.

Abstract: An arithmetic unit, for example a multiply and accumulate (MAC) unit 42, for a processing engine includes a partial product reduction tree 480. The partial product reduction tree will generate carry results and provides a final output to a final adder 470 connected to the partial production reduction tree. Unbiased rounding logic 476 is provided. A carry propagation tree is responsive to the carry results for anticipating a zero on each of N least significant bits of the final adder. When zero is anticipated on each of N least significant bits of the final adder, the carry propagation tree is operable to generate an output signal 477 which is used by the unbiased rounding stage to force the (N+1)th least significant bit of the final adder to zero.

Abstract: A methodology of signal estimation over the generalized fading channel can be applied to any parameter whose dB value is required to be estimated. The estimator is shown to be asymptotically efficient in a number of samples and the amount of fading. Theoretical and simulation results confirm that the SINR estimator implemented using the methodology outperforms the sample-average estimator, which is currently used in most of systems and robust to the channel variation.

Abstract: The present invention facilitates semiconductor fabrication by maintaining uniform thickness of a gate oxide layer (112) during the oxide growth process of non-volatile memory devices (100). The uniform thickness of a gate oxide layer (112) is obtained by defining the boundaries of the source and drain areas (110) of a memory device (100) with the source/drain dopant masking and implanting operation. If an isolation barrier (108) is present it is kept a minimum safe distance (130) away from the periphery of the conductive gate layer (114) to avoid birds-beak regions (30) responsible for non-uniform gate oxide growth. As a result, the corresponding charge losses and weak cells are mitigated, thereby facilitating the fabrication of more reliable memory cells (100). Because a more uniform gate oxide thickness (112) is used in association with the memory cells (100), a single significantly thinner gate oxide layer (114) may be employed throughout the memory device (100).

Abstract: A method and apparatus to reduce the amount of required memory and instruction cycles when implementing Fast Fourier Transforms (FFTs) on a computer system is described. The invention optimizes FFT software using in-place bit reversal (IPBR) implemented on a processor capable of bit reversed incrementation. Alternative embodiments implement the invention for out of place bit reversal (OOPBR) and on processors that do not support special instructions for bit reversed incrementation. The invention only generates unique bit-reversed address pairs and avoids generation of self-reversed addresses. To optimize the invention for in place bit reversal, every non-self bit reversed address in the input array is generated only once, while making simple, computationally efficient increments away from the previous pair of bit reversed addresses. The address pair generator can independently advance only one address in each address pair, and bit reversal of one address uniquely defines the other address.

Abstract: Devices being controlled electronically via physical manipulation often display a resonance. In many circumstances, the frequency range of operation is not close to the resonance frequency. In these cases, the resonance can be removed through the use of simple compensation techniques such as filters. However, when the resonance frequency is close to the frequency range of operation and when the resonance frequency can change depending on temperature, time, and physical position of the device, simple compensation techniques cannot be used. The present invention presents a non-mechanical technique for providing compensation for devices with a shifting resonance. The non-mechanical technique allows for the compensation to be performed via computation.

Abstract: A method (200) of forming an isolation structure is disclosed, and includes forming a patterned isolation hard mask layer (206, 212) having an isolation opening associated therewith over a semiconductor body. An implant into the isolation opening is then performed (214), followed by forming an isolation trench (216) in the semiconductor body associated with the isolation opening. The isolation trench is then filled with a dielectric material (218).

Abstract: A technique and circuit is provided for facilitating a faster settling time for a digital filter for use with an analog-to-digital converter. An exemplary technique utilizes a composite filter for a faster settling, lower noise resolution filter in a parallel configuration with a slower settling, higher noise resolution filter. As a result, valid data can be received faster for processing by the analog-to-digital converter. In addition, a composite digital filter circuit can include a three filter configuration including a fast-settling, low resolution first filter, a slower-settling, higher resolution second filter, and an even slower-settling, even higher resolution third filter, each of the filters configured in a parallel arrangement. Additional or fewer filters can also be provided. Moreover, the gain of each filter path can be suitably matched to the gain of any other filter path in the digital filter circuit to provide a filter output having an equalized gain regardless of the filter path selected.