Patents Assigned to Texas Instruments
  • Publication number: 20060081894
    Abstract: A method of forming an integrated circuit transistor (50). The method provides a first semiconductor region (52) and forms (110) a gate structure (54x) in a fixed position relative to the first semiconductor region. The gate structure has a first sidewall and a second sidewall (59x). The method also forms at least a first layer (58x, 60x) adjacent the first sidewall and the second sidewall. The method also forms (120) at least one recess (62x) in the first semiconductor region and extending laterally outward from the gate structure. Additional steps in the method are first, oxidizing (130) the at least one recess such that an oxidized material is formed therein, second, stripping (140) at least a portion of the oxidized material, and third, forming (160) a second semiconductor region (66x) in the at least one recess.
    Type: Application
    Filed: October 18, 2004
    Publication date: April 20, 2006
    Applicant: Texas Instruments Incorporated
    Inventor: Lindsey Hall
  • Patent number: 7029967
    Abstract: A method for forming metal silicide regions in source and drain regions (160, 170) is described. Prior to the thermal annealing of the source and drain regions (160, 170), germanium is implanted into a semiconductor substrate adjacent to sidewall structures (90, 95) formed adjacent gate structures (60, 70). The position of the implanted germanium species in the semiconductor substrate will overlap the source and drain regions (160, 170). Following thermal annealing of the source and drain regions (160, 170), the implanted germanium prevents the formation of metal silicide spikes.
    Type: Grant
    Filed: July 21, 2004
    Date of Patent: April 18, 2006
    Assignee: Texas Instruments Incorporated
    Inventors: Song Zhao, Sue E. Crank, Amitava Chatterjee, Kaiping Liu, Jiong-Ping Lu, Donald S. Miles, Duofeng Yue, Lance S. Robertson
  • Patent number: 7032159
    Abstract: A method is disclosed for providing data for automatically estimating channel performance if different parameters of a Reed-Solomon (RS) code are used in a communication system while transmission is occurring in the communication system without changing the current Reed-Solomon (RS) code parameters.
    Type: Grant
    Filed: October 18, 2002
    Date of Patent: April 18, 2006
    Assignee: Texas Instruments Incorporated
    Inventors: Itay Lusky, Daniel Wajcer, Yosef Bendel, Yigal Bitran, Naftali Sommer, Ofir Shalvi, Zvi Reznic, Ariel Yagil, Eli Haim
  • Patent number: 7031374
    Abstract: A RAKE receiver with demodulating fingers is presented having the capability to assign a specific sample stream, from among a plurality of received sample streams, to any of the demodulating fingers. The demodulating finger includes a MUX to receive the plurality of sample streams. Commands from a controller to the MUX of a demodulating finger select a specific sample stream to be demodulated by that demodulating finger. Since each demodulating finger receives all the sample streams, and any sample stream can be selected, the receiver has the flexibility of optimally varying the assignment of demodulating fingers to sample streams. A method for selecting a sample stream for demodulation, from among a plurality of sample streams, is also provided.
    Type: Grant
    Filed: October 6, 2000
    Date of Patent: April 18, 2006
    Assignee: Texas Instruments Incorporated
    Inventor: John G. McDonough
  • Patent number: 7031163
    Abstract: In one embodiment, an integrated circuit includes an electrically active interconnect line within a dielectric layer having a top and bottom surface, the bottom surface of the dielectric layer being coupled to the top surface of a substrate underlying the dielectric layer. The dielectric layer has horizontally arranged heat dissipating layers. An electrically inactive conductor or cooling fin is located within the dielectric layer at a heat dissipating layer below and closer to the substrate than said active interconnect line. The electrically inactive conductor is coupled to said electrically active interconnect line as an extensions of electrically active interconnect line to dissipate heat therefrom.
    Type: Grant
    Filed: October 17, 2003
    Date of Patent: April 18, 2006
    Assignee: Texas Instruments Incorporated
    Inventors: Ki-Don Lee, Srikanth Krishnan, William R. Hunter
  • Patent number: 7031916
    Abstract: A method of initializing an ITU Recommendation G.729 Annex B voice activity detection (VAD) device is disclosed, having the steps of (1) extracting a set of parameters from a signal that characterize the signal; (2) calculating an energy measure of the signal from the set of parameters; (3) comparing the energy measure with a reference value; (4) determining an initial value for an average of a noise characteristic of the signal; and (5) counting the number of times the energy measure equals or exceeds the reference level. Also disclosed is a method of converging an ITU Recommendation G.
    Type: Grant
    Filed: June 1, 2001
    Date of Patent: April 18, 2006
    Assignee: Texas Instruments Incorporated
    Inventors: Dunling Li, Daniel C. Thomas, Gokhan Sisli
  • Patent number: 7029925
    Abstract: The present invention is directed to a method of forming an FeRAM integrated circuit, which includes performing a capacitor stack etch to define the FeRAM capacitor. The method comprises etching a PZT ferroelectric layer with a high temperature BCl3 etch which provides substantial selectivity with respect to the hard mask. Alternatively, the PZT ferroelectric layer is etch using a low temperature fluorine component etch chemistry such as CHF3 to provide a non-vertical PZT sidewall profile. Such a profile prevents conductive material associated with a subsequent bottom electrode layer etch from depositing on the PZT sidewall, thereby preventing leakage or a “shorting out” of the resulting FeRAM capacitor.
    Type: Grant
    Filed: October 19, 2004
    Date of Patent: April 18, 2006
    Assignee: Texas Instruments Incorporated
    Inventors: Francis G. Celii, Scott R. Summerfelt, Mahesh Thakre
  • Patent number: 7030038
    Abstract: This invention pertains generally to forming thin oxides at low temperatures, and more particularly to forming uniformly thick, thin oxides. We disclose a low temperature method for forming a thin, uniform oxide 16 on a silicon surface 12. This method includes providing a partially completed integrated circuit on a semiconductor substrate 10 with a clean, hydrogen terminated or atomically flat, silicon surface 12; and stabilizing the substrate at a first temperature. The method further includes exposing the silicon surface to an atmosphere 14 including ozone, while maintaining the substrate 10 at the first temperature. In this method, the exposing step creates a uniformly thick, oxide film 16. This method is suitable for room temperature processing.
    Type: Grant
    Filed: October 21, 1998
    Date of Patent: April 18, 2006
    Assignee: Texas Instruments Incorporated
    Inventors: Glen D. Wilk, Robert M. Wallace, Berinder P. S. Brar
  • Patent number: 7031379
    Abstract: A method for deriving coefficients for a time domain equalizer function (24) as implemented by a digital signal processor (35) in a DSL modem (20) is disclosed. A transmitting modem (10), such as at a central office, issues a pseudo-random training sequence that is received by the receiving modem (20). Correlation matrices are derived by the digital signal processor (35), from which sets of eigenvalues and eigenvectors are derived. A flatness constraint on the frequency response of the time domain equalizer is established, and included with a flatness scaling factor (?) into a minimization cost function. One or more values of the flatness scaling factor (?), preferably between minimum and maximum eigenvalues, are evaluated in the cost function, to derive the optimum filter for the time-domain equalizer. The flatness constraint ensures that the time-domain equalizer is not subject to near null conditions and large variations in its frequency response.
    Type: Grant
    Filed: August 24, 2001
    Date of Patent: April 18, 2006
    Assignee: Texas Instruments Incorporated
    Inventors: Charles K. Sestok, IV, Nirmal C. Warke
  • Patent number: 7030792
    Abstract: A digital-to-analog converter (DAC) error suppression arrangement suppresses DAC error arising from mismatched elements contained in a DAC (640 and/or 645) that is part of a modulator (FIG. 6). A low pass averaging (LPA) index decoder 650 controls a shifting arrangement 635 to shift a digital word T2 derived from modulator output Y so that the DAC error distribution constitutes a low pass profile (FIG. 5). Thus, DAC error is suppressed at higher frequencies (close to half the sampling rate), thereby providing improved spurious free dynamic range (SFDR). The LPA index decoder 650 causes the shifting arrangement 635 to shift the digital word T2 using only a single pointer per clock cycle.
    Type: Grant
    Filed: September 28, 2005
    Date of Patent: April 18, 2006
    Assignee: Texas Instruments Incorporated
    Inventor: Feng Chen
  • Patent number: 7031863
    Abstract: Signal conditioning of multiple sense elements is shown for providing information to a system requiring high accuracy and robust fault coverage. A first signal conditioning ASIC (10) pre-conditions the sense element data and a second system control ASIC (14) mathematically solves predetermined compensation relations based on the output of ASIC (10) and stored compensation data to fully condition the sensor output signal(s). The sense elements (1–6) are each formed by two half bridges whose inputs are pre-conditioned by separate, identical signal conditioning paths to provide highly accurate sense and diagnostic information.
    Type: Grant
    Filed: December 22, 2003
    Date of Patent: April 18, 2006
    Assignee: Texas Instruments Incorporated
    Inventors: Thomas R. Maher, David L. Corkum
  • Patent number: 7030659
    Abstract: An electronic switch applies ground potential to the backgate of a MOS pass transistor when the transistor is in the off state and the switch is open, during normal conditions. When the transistor is switched to the on state and the switch is closed, the gate voltage is applied to the backgate of the pass transistor in order to reduce the threshold voltage and the on resistance. During an undershoot condition, the gate of the pass transistor is connected to the negative voltage applied to an input port and this voltage is also connected to the backgate of the pass transistor to prevent the pass transistor from being biased on or the parasitic NPN transistor from being biased on and transmitting the input glitch to the output.
    Type: Grant
    Filed: August 24, 2004
    Date of Patent: April 18, 2006
    Assignee: Texas Instruments Incorporated
    Inventor: Christopher M. Graves
  • Patent number: 7029972
    Abstract: The present invention provides method of manufacturing a metal-insulator-metal capacitor (100). A method of manufacturing includes depositing a first refractory metal layer (105) over a semiconductor substrate (110). The first refractory metal layer (105) over a capacitor region (200) of the semiconductor substrate (110) is removed and a second refractory metal (300) is deposited over the capacitor region (200). Other aspects of the present invention include a metal-insulator-metal capacitor (900) and a method of manufacturing an integrated circuit (1000).
    Type: Grant
    Filed: July 20, 2004
    Date of Patent: April 18, 2006
    Assignee: Texas Instruments Incorporated
    Inventors: Tony Thanh Phan, Farris D. Malone
  • Patent number: 7029932
    Abstract: Parametric testing of an integrated circuit chip includes pressing first, second, and third contact elements (PRB-1,2,3) against first, second and third terminals (P1–3), respectively, of the integrated circuit and forcing first, second, and third reference currents (Iref) through first, second, and third circuit paths each including a corresponding ESD diode. Each path includes two of the contact elements, two associated contact resistances, and one of the ESD diodes. First, second, and third voltages (Vm1–3) are measured across the three circuit paths. Three equations representative of the three voltages are simultaneously solved to determine three contact resistances between the various contact elements and integrated circuit terminals. The voltages across the three contact resistances are computed by multiplying them by parametric test currents and are added to or subtracted from measured voltages of the contact elements to obtain accurate values of voltages of the integrated circuit terminals.
    Type: Grant
    Filed: February 7, 2005
    Date of Patent: April 18, 2006
    Assignee: Texas Instruments Incorporated
    Inventors: Daryl T. Hiser, Stephen J. Sanchez
  • Patent number: 7031457
    Abstract: A digital input signal is analyzed by a peak detector (210) configurable to trigger a first logic signal (260) if the peak detector detects the digital input signal level crossing a certain threshold. The threshold value can be modified by an overhead. The amplifier (250) employs a plurality of supply rails of differing voltages (253, 255) as a function of the logic signals. A digital signal delay element (220) may delay the signal to allow sufficient time for the amplifier to switch between supply sources. A logic delay element (280) may delay transmittal of the first logic signal by the peak detector to compensate for signal delay caused by a filter. A hold element (270) ensures that the first logic signal is applied to the output amplifier for a given amount of time.
    Type: Grant
    Filed: November 30, 2001
    Date of Patent: April 18, 2006
    Assignee: Texas Instruments Incorporated
    Inventor: Peter J. Melsa
  • Patent number: 7028396
    Abstract: A process and tooling for removing a semiconductor chip (31) from a handling tape (321) without damage to either the chip or tape by one or more horizontal beam type ejector tools (333) driven by a variable speed motor (332) applying uniform pressure to the tape and chip backside. Each tool (333) emerges from a rigid support surface through an aperture which also serves to supply vacuum to hold the chip in alignment prior to ejection, and in turn allows planar removal of the chip by a pick-up arm (351).
    Type: Grant
    Filed: April 14, 2003
    Date of Patent: April 18, 2006
    Assignee: Texas Instruments Incorporated
    Inventor: Iszharudin Hassan
  • Patent number: 7031380
    Abstract: A multi-client ADSL modem network (10) that can be configured for a home or office network when multiple ADSL client modems (18) are installed in different communication terminals (22). One ADSL modem (14) at a central office (12) coordinates the remote multi-client modems (18) for communication over a single twisted pair loop carrier phone line (16), allowing the connected modems (18) to communicate not only with the CO modem (14), but also with each other by sharing frames, tones, or by code division techniques on upstream channels. The CO modem (14) operates as a network hub and/or arbitrator, and facilitates one ADSL modem to become the master modem and maintain a superframe. The present invention provides home network ADSL service without extra wiring or equipment, thus providing a low cost approach for home networking of ADSL service.
    Type: Grant
    Filed: August 31, 2000
    Date of Patent: April 18, 2006
    Assignee: Texas Instruments Incorporated
    Inventors: Yaqi Cheng, Yaser M. Ibrahim, Song Wu
  • Patent number: 7031400
    Abstract: Disclosed are methods of selecting a multi-dimensional signal constellation in relation to impairments in a communication system having a data frame consisting of a fixed number of symbols. The methods make use of impairments detected from a Digital Impairment Learning sequence (DIL) and channel impairments, such as POE and SNR. Signal points are individually assigned to each symbol in a data frame in relation to that symbol's particular digital impairments and a pre-selected minimum performance level and maximum power constraints.
    Type: Grant
    Filed: March 20, 2002
    Date of Patent: April 18, 2006
    Assignee: Texas Instruments Incorporated
    Inventors: Nirmal C. Warke, Murtaza Ali
  • Patent number: 7032204
    Abstract: Disclosed are systems, methods, and algorithms for network layout. A network layout having subnetworks of matching series and parallel elements is systematically generated to implement the network within area constraints. After the selection of the number of rows of network elements, the number of elements in each row, the sequencing of the elements, and the element locations, are systematically determined. The network layout systematically produced reduces the influence of unfavorable factors on the network such as temperature gradients, process gradients, and interference, by dispersing subnetwork elements throughout the layout.
    Type: Grant
    Filed: June 8, 2004
    Date of Patent: April 18, 2006
    Assignee: Texas Instruments Incorporated
    Inventors: David Jaska, Tan Du
  • Patent number: 7026833
    Abstract: A probe card assemblage for simultaneously testing one or more integrated circuit chips including an interposer having on one surface a plurality of protruding contact elements for electrically contacting one or more chips of a wafer positioned atop a layer of compliant material, and arrayed in a pattern corresponding to a chip pads, a series of conductive vias through the electrically insulating interposer which connect the chip contact elements with an arrangement of leads terminating in a universal arrangement of connectors on the second surface, and a probe card with connectors mating to those on the interposer. The connectors on the interposer is secured are secured to those on the probe card, thereby providing a vertical probe assemblage which makes use of ultrasonic energy to minimize scrub or over travel. The universal probe card is specific to a tester configuration and common to a family of circuits to be tested.
    Type: Grant
    Filed: August 26, 2005
    Date of Patent: April 11, 2006
    Assignee: Texas Instruments Incorporated
    Inventors: Reynaldo M. Rincon, Richard W. Arnold