Abstract: The present invention provides improved line and load regulation of a switching-mode power converter (300) without requiring additional capacitors (255), either internally or externally, to stabilize the control loop. The present invention can provide this by integrating a digital compensator (375) with the pulse-width modulator (“PWM”) of the switching-mode power converter. Such a compensator (375) can include comparators (310 and 330), digital circuits (340), and resistors (215, 220, 320, and 325).

Abstract: Systems and methods for providing a wireless communication device with secure terminal identity information and secure collaborative terminal identity authentication between the wireless communication device and a wireless operator. In one embodiment, the system for providing a wireless communication device with secure terminal identity information includes: (1) a public key generator configured to generate a unique public key and a unique private key based on an identity of the wireless communication device and cause the private key to be stored within a secure execution environment of the wireless communication device and (2) a certificate generator coupled to the public key generator and configured to create a device-bound certificate based on the identity and cause the device-bound certificate to be stored within the secure execution environment.

Abstract: Maintaining synchronization when sending/receiving multiple channels of data with a corresponding common reference clock signal. Synchronization signals (e.g., pulses) are generated periodically and the timing of channels is adjusted. In an embodiment, multiple sequences of parallel data elements are received on corresponding parallel data channels using a first common clock signal. Each sequence of parallel data elements is converted to a corresponding sequence of serial data elements. The serial data elements are transmitted on a corresponding serial channel using a serial clock as a common reference. A synchronization signal may be generated periodically with a time period of (the number of bits in each parallel data element x the time period of the serial clock), wherein ‘x’ represents multiplication operation. As the parallel data channels are synchronized in short intervals, synchronization is maintained.

Abstract: A synchronizer circuit which synchronizes an input clock signal to a sampling clock to generate a synchronized signal. In an embodiment, an adaptive module detects the occurrence of a positive edge in an input clock signal after a logic low corresponding to a prior negative edge is propagated to as a synchronized signal, and provides a logic high as an input to a sampling module. The sampling module propagates the signal level at the input as the synchronized signal. The adaptive module causing the input to remain at logic high at least until the synchronization module provides logic level as the synchronized signal. The negative edges in the input signal may also be processed similarly.

Abstract: An electronic device (10). The device comprises means (14) for displaying a compass directional bearing. The device also comprises means (18, 26, CAM) for determining the compass directional bearing unresponsive to a local magnetic field in which the electronic device is located, wherein the means for determining comprises image capturing circuitry.

Abstract: A client premises digital subscriber line (DSL) modem having multi-mode capability is disclosed. In initialization, the modem estimates whether channel conditions are such that digital processing of the received data according to a lower data rate DSL standard, such as ADSL2, may result in a higher effective data rate than receipt and processing according to a higher data rate DSL standard, such as ADSL2+. If so, the DSL modem configures itself, such as by configuring its filter characteristics and sampling frequency, to receive and process data according to the lower data rate DSL standard; the transmitting modem, for example at a central office or service area interface, may continue to operate according to the higher data rate standard (with its bit loading corresponding to a subset of subchannels). The receiving DSL modem processes the payload data according to the lower standard, while processing control messages according to the higher standard.

Abstract: An electronic system. The system comprises a plurality of circuit paths. Each path in the plurality of circuit paths is coupled to receive a system voltage from a voltage supply. The system further comprises a first circuit for providing a first value indicating a potential capability of operational speed of at least one path in the plurality of paths and a second circuit for providing a second value for indicating a potential capability of operational speed of the at least one path in the plurality of paths. The system further comprises circuitry for adjusting the system voltage, as provided by the voltage supply, in response to a relation between the first value and the second value.

Abstract: A wireless communications device is disclosed, in which certain digital coding functions are realized according to a modified multiplier architecture. The device includes an encode and modulate function within which convolutional coding function is provided. The convolutional coding function may be realized as a modified parallel multiplier, in which carries among adder units are ignored or not generated. The datastream is applied to the multiplier as the multiplicand, while successive sets of code generator polynomial coefficients are applied as a multiplier. Carry-in and carry-out bits among the adder units are blocked in a coding mode, but passed in a multiplier mode. A similar arrangement of a modified parallel multiplier circuit may be used in generating a scrambling code that is applied prior to transmission.

Abstract: A solid state motor protector has a first PTC chip (positive temperature coefficient of resistivity) electrically connected in series relation with a second resistor having a generally fixed temperature coefficient of resistivity and mechanically coupled to the first resistor in close/direct thermal coupling. Another embodiment has a plate like isolator (52) formed with an opening receiving a polymer PTC chip (58) and having terminals (54, 56) which serve as fixed resistors. Yet another embodiment has an additional PTC resistor and a fixed resistor used in a motor reversing mechanism. Still another embodiment has a fixed resistor on either side of a PTC resistor for use in protecting the windings of a single phase motor. Another embodiment has a stack of polymer PTC resistor chips (82a–82d) with one chip serving as a voltage blocking chip and the other chip serving as fixed resistors.

Abstract: Devices and methods are disclosed related to a bipolar transistor device and methods of fabrication. A top region is formed at a surface of and within a base region. The top region is formed by implanting a dopant of an opposite conductivity to that of the base region. However, the top region remains of the same conductivity type as the base region (e.g., n-type or p-type). This implanting, also referred to as counterdoping, increases resistivity of the top region and thus improves an emitter-base breakdown voltage. Additionally, this implanting does not have a substantial detrimental affect on a beta value, also referred to as an amplification property, or a collector emitter breakdown voltage, also referred to as BVceo, for the transistor. The beta value and the collector emitter breakdown voltage are mainly a function of a bottom portion of the base region.

Abstract: A thermally enhanced BGA semiconductor device 10 having a heat sink 12 formed from a single piece of material with an expanded base and a pedestal in contact with a semiconductor chip 11. The pedestal is aligned through a window opening in a substrate 13 and the top surface of the base is adhered to the substrate. The heat sink 12 with an expanded base provides a path for rapid and efficient heat spreading and dissipation, a stand-off and an aid to improved package planarity during reflow to a PCB, and a long path for ingress of contaminants into the package. The device is amenable to high volume, low cost production.

Abstract: A system and method is provided for monitoring interference in a wireless communication system. The system and method monitor error statistic data at one or more devices in a wireless communication system. The error statistic data can be utilized to determine the location of the interference. If any unusual error statistic data is present at the one or more of the devices, raw unprocessed data is provided from the devices experiencing unusual error activity. The raw unprocessed data can be utilized to characterize the interference. For example, the raw unprocessed data can be compared to one or more interference templates to determine an interference type. The raw unprocessed data can be compared between devices in the wireless communication system to determine the location of the interference with increased precision.

Abstract: Configuration data is stored in one or more rows of non-volatile ferroelectric memory cells, where these rows are formed adjacent to rows of a primary memory array. The primary memory array includes non-volatile ferroelectric memory cells, and the memory cells of the array are substantially the same in construction to the cells of the configuration data rows. This allows at least some of the circuitry utilized to access data from the primary array to be utilized to access the configuration data, which promotes an efficient use of resources among other things. Additionally, the configuration data can be transferred to volatile registers serially at startup to simplify routing and design and thereby conserve space. The volatile registers are operatively associated with configuration data circuitry that makes use of the configuration data at startup or later time(s).

Abstract: A method that allows an optical wireless communication link between transmitting and receiving stations to be established and used reliably without the need for position sensing capabilities. A small random nudge of the center of the acquisition spiral is used to prevent a link from being established before proper alignment is attained or to correct the alignment of an established link which does not have sufficient alignment to maintain a high bandwidth link.

Abstract: An integrated circuit includes an external reset input, a clock input for receiving a clock signal and a reset signal sub-circuit including an internal reset output connected to other circuits of the integrated circuit. The reset signal sub-circuit immediately supplies an internal reset signal upon receipt of the external reset signal and ceases to supply the internal reset signal upon a next clock signal following ceasing to receive the external reset signal. This asynchronously forces combinational logic to a reset state upon receipt of the internal reset signal and synchronously forces sequential logic to a reset state upon receipt of a next clock signal.

Abstract: Linear predictive speech coding system with classification of frames and a hybrid coder using both waveform coding and parametric coding for different classes of frames. Phase alignment for a parametric coder aligns synthesized speech frames with adjacent waveform coder synthesized frames. Zero phase alignment of speech prior to waveform coding aligns synthesized speech frames of a waveform coder with frames synthesized with a parametric coder. Inter-frame interpolation of LP coefficients suppresses artifacts in resultant synthesized speech frames.

Abstract: A memory device (20) having substantially reduced leakage current in a sleep/data retention mode whereby at least a portion (25, 28) of the periphery circuitry (24) shares the same power supplies VDDA and/or VSSA of the memory array (22) such that during sleep/data retention mode the voltage across both the portion (25, 28) of the periphery circuitry (24) and the memory array (22) of the selected SRAM block is reduced, while all other circuits can be shut down except the sleep control circuits as well as selected latches, flip-flops, etc. whose contents need to be retained. A sequence for powering up and shutting down portions of the periphery circuitry (24) and the external circuitry (26) is also provided.

Abstract: A method for processing data using a multiplexing architecture includes performing a selected one of a plurality of first multiplexer operations on the data and then a selected one of a plurality of second multiplexer operations. The first multiplexer operations include a pass operation and a plurality of bit rearrangement operations. The second multiplexer operations include a pass operation and a plurality of bit duplication operations which duplicates a selected bit or bits to a corresponding block of contiguous bits in the output. A result is then generated that reflects the outputs produced by first and second multiplexers respectively.

Abstract: The invention relates to a method for transparently maintaining cache coherency when debugging a multiple processor system with common shared memory. A software memory map representing the memory usage of the processors in the system to be debugged is created and in the software memory map is an indication of whether or not each processor has a cache. At least two debug sessions associated with two processors are activated. If an active debug session requests a write to a shared memory location, the request is executed and the software memory map is searched to located all processors having read access to that shared memory location. The write request is broadcast to each of the located processors so that each processor can perform any required cache updates.

Abstract: A wireless local area network (LAN) adapter (20) that optimizes the length of message packets, for example according to the IEEE 802.11 standard, and in an environment having interfering transmissions (BL1 et seq.), is disclosed. The disclosed adapter (20) executes an adaptive process by way of which an adjustment to the packet length is derived based upon rate measures for the most recent two trial packet lengths. The rate measure corresponds to a packet success rate for that packet length, determined either from an estimating function or by actual measurements, multiplied by a ratio of the data portion of each packet to a total packet length including interpacket spacing. Upon convergence as the adjustment becomes smaller, the optimized packet length for best data rate given the present interference. A method of determining the need for packet length optimization is also disclosed, in which the actual packet error rate is compared against an expected packet error rate based upon signal-to-noise ratios.