Patents Assigned to Texas Instruments
  • Method for improved cu electroplating in integrated circuit fabrication
    Patent number: 6784104
    Abstract: The electroplating of copper is the leading technology for forming copper lines on integrated circuits. In the copper electroplating process a negative potential is applied to the semiconductor wafer with the surface of the semiconductor wafer acting as the cathode. The anode will be partially or wholly formed with copper. Both the anode and the semiconductor will be exposed to a solution comprising copper electrolytes. By reducing the temperature of the copper electrolytes solution below 25° C. the rate of self annealing grain growth will increase reducing the final resistively of the copper lines.
    Type: Grant
    Filed: July 12, 2002
    Date of Patent: August 31, 2004
    Assignee: Texas Instruments Incorporated
    Inventors: Qing-Tang Jiang, Jiong-Ping Lu
  • Apparatus and method for indicating a difference between first and second voltage signals
    Patent number: 6784736
    Abstract: An apparatus for indicating a difference between a first voltage and a second voltage includes: (a) an input unit for receiving the first voltage at a first locus and receiving the second voltage at a second locus; the input unit quanitifying the difference; (b) an output unit coupled with the input unit and cooperating with the input unit to generate an output signal for effecting the indicating; and (c) a signal treating unit coupled with the output unit, the first locus and the second locus, and employing at least one algorithmic relation with at least one of the first voltage and the second voltage to generate at least one bias current for effecting a substantially balanced response by said output section in said generating said output signal as said difference varies. The at least one drive current has nonnegative values as the difference ranges in value.
    Type: Grant
    Filed: November 12, 2002
    Date of Patent: August 31, 2004
    Assignee: Texas Instruments Incorporated
    Inventor: Charles Parkhurst
  • Integrated circuit dielectric and method
    Patent number: 6784121
    Abstract: A xerogel aging system includes an aging chamber (190) with inlets and outlet and flows a gel catalyst in gas phase over a xerogel precursor film on a semiconductor wafer. Preferred embodiments use an ammonia and water vapor gas mixture catalyst.
    Type: Grant
    Filed: October 23, 1998
    Date of Patent: August 31, 2004
    Assignee: Texas Instruments Incorporated
    Inventors: Changming Jin, Richard Scott List, Joseph D. Luttmer
  • Thermally enhanced semiconductor chip having integrated bonds over active circuits
    Patent number: 6784539
    Abstract: An integrated circuit (IC) chip has a metal network of electrical power distribution lines which have a thermal conductance at least an order of magnitude greater than underlying thin film electrical interconnects. These lines are deposited on the surface of the chip (FIG. 2), located directly over active IC components, and electrically and thermally connected vertically to selected active components below the lines. Electrical conductors are operable to connect the lines to an outside source, and additional electrically non-functional conductors are distributed on the lines, operable to steepen the thermal gradient for thermal flux away from said active components and lines.
    Type: Grant
    Filed: June 25, 2003
    Date of Patent: August 31, 2004
    Assignee: Texas Instruments Incorporated
    Inventor: Taylor R. Efland
  • Compact, high power supply rejection ratio, low power semiconductor digitally controlled oscillator architecture
    Patent number: 6784755
    Abstract: A high PSRR, low power semiconductor digitally controlled oscillator (DCO) architecture employs only one simple current steering D/A converter directly on top of a multi-stage current controlled oscillator. The architecture provides a good building block for many circuit applications, e.g., all digital phase lock loops, direct modulation transmitters for wireless devices, and the like.
    Type: Grant
    Filed: November 12, 2002
    Date of Patent: August 31, 2004
    Assignee: Texas Instruments Incorporated
    Inventors: Heng-Chih Lin, Baher S. Haroun
  • Interleaver for variable block size
    Patent number: 6785859
    Abstract: An interleaver structure for turbo codes with variable block size. The interleaver permutes symbols through multiplication by a parameter followed by modulus by the block size. A table of the multiplication parameter as a function of the block size permits adaptability to a wide range of block sizes without significant memory consumption.
    Type: Grant
    Filed: August 6, 2001
    Date of Patent: August 31, 2004
    Assignee: Texas Instruments Incorporated
    Inventor: Haim Goldman
  • Compact image sensor layout with charge multiplying register
    Patent number: 6784412
    Abstract: The image sensing device incorporates a charge multiplication function in its serial register. The design layout is compact in size and the charge multiplication register consists of multi-channel sections that are evenly positioned around the periphery of the image sensing area. The individual charge multiplying register sections are coupled together by only 90-degree multi-channel turns located at the image area array corners. The device allows for the optical image sensing area center to be located near the chip center and consequently near the mechanical package center with the minimum silicon chip area sacrifice.
    Type: Grant
    Filed: August 12, 2002
    Date of Patent: August 31, 2004
    Assignee: Texas Instruments Incorporated
    Inventor: Jaroslav Hynecek
  • Gate structure and method
    Patent number: 6784507
    Abstract: CMOS and BiCMOS structures with a silicate-germanate gate dielectric on SiGe PMOS areas and Si NMOS areas plus HBTs with Si—SiGe emitter-base junctions.
    Type: Grant
    Filed: September 27, 2002
    Date of Patent: August 31, 2004
    Assignee: Texas Instruments Incorporated
    Inventors: Robert M. Wallace, Bruce E. Gnade
  • Method of dicing a semiconductor wafer and heat sink into individual semiconductor integrated circuits
    Patent number: 6784022
    Abstract: A method of producing semiconductor devices including the steps of providing a semiconductor wafer of substantially uniform thickness 22, providing a heat-radiating plate 22, and attaching the heat-radiating plate 20 to the semiconductor wafer. The assembled wafer and heat-radiating plate are diced into individual semiconductor integrated circuits having individual heat radiating plates attached thereto.
    Type: Grant
    Filed: April 11, 2002
    Date of Patent: August 31, 2004
    Assignee: Texas Instruments Incorporated
    Inventors: Norito Umehara, Masazumi Amagai
  • Folded monopole antenna, bent, tapped, or both, and systems incorporating same
    Publication number: 20040166908
    Abstract: Various antenna designs that are small and cost effective are disclosed. In one design, the antenna is a bent and folded monopole antenna. In another design, the antenna is a folded and tapped monopole antenna. In yet another design, the antenna is a folded, bent, and tapped monopole antenna. The antennas may be part of a system using two back-to-back symmetric antennas. The antennas may be part of a modem, such as a wireless computer modem or a wireless handset.
    Type: Application
    Filed: November 19, 2003
    Publication date: August 26, 2004
    Applicant: Texas Instruments Incorporated
    Inventor: A. J. McInnis
  • Characterizing an exposure tool for patterning a wafer
    Publication number: 20040167748
    Abstract: Characterizing an exposure tool involves receiving data describing a pattern formed at a wafer. The pattern is formed by illuminating the wafer using an exposure tool, and the data has a scan direction and slit direction. An image field is mapped according to the data to determine an image field error of the data, and the image field error is separated from the data to reduce variation of the data in the scan direction. The data is reduced to the slit direction. Errors associated with the exposure tool are determined from the data in order to characterize the exposure tool.
    Type: Application
    Filed: February 21, 2003
    Publication date: August 26, 2004
    Applicant: Texas Instruments Incorporated
    Inventors: Guohong Zhang, Changan Wang, Stephen J. DeMoor
  • Undulated moat for reducing contact resistance
    Patent number: 6780742
    Abstract: The present invention includes a method of forming a semiconductor device.
    Type: Grant
    Filed: July 3, 2003
    Date of Patent: August 24, 2004
    Assignee: Texas Instruments Incorporated
    Inventor: Christoph Wasshuber
  • Selective deposition of emissive layer in electroluminescent displays
    Patent number: 6780662
    Abstract: A method for forming an emissive layer for an electroluminescent display is provided that includes positioning a substrate (40) in spaced relation to a port (88) of a microeffusion cell (86). The method then provides for transporting the substrate (40) across the port (88) at a substantially constant rate. The method then provides for effusing an emissive material from the port (88) and adhering at least a portion of the emissive material effused from the port (88) to a defined region of the substrate (40) to form an emissive strip (46) having a substantially constant width on the substrate (40).
    Type: Grant
    Filed: July 23, 2003
    Date of Patent: August 24, 2004
    Assignee: Texas Instruments Incorporated
    Inventor: Leland S. Swanson
  • Spreading the power dissipation in MOS transistors for improved ESD protection
    Patent number: 6781204
    Abstract: An MOS transistor in the surface of a semiconductor substrate (180) of a first conductivity type, which has a grid of isolations (171) in the surface, each grid unit surrounding a rectangular substrate island (102). Each island contains two parallel regions of the opposite conductivity type: one region (174) is operable as the transistor drain and the other region (173) is operable as the transistor drain, each region abutting the isolation. A transistor gate (105) is between the parallel regions, completing the formation of a transistor. Electrical contacts (106) are placed on the source region (173) so that the spacing (120) between each contact and the adjacent isolation is at least twice as large as the spacing (121) between each contact and the gate. A plurality of these islands are interconnected to form a multi-finger MOS transistor.
    Type: Grant
    Filed: March 13, 2003
    Date of Patent: August 24, 2004
    Assignee: Texas Instruments Incorporated
    Inventors: Charvaka Duvvury, Kwang-Hoon Oh
  • Capacitive pressure transducer
    Patent number: 6781814
    Abstract: A capacitive fluid pressure transducer (10′) has a sensing element (12) received in an electrically conductive cup-shaped shield member (24) which is crimped onto the base of an electrical connector (20′). A conditioning circuit (14) is received in a circuit chamber formed between the sensor element and the connector and is provided with a tab carrying a conductive trace for electrical connection of the shield member with the circuit. The shield member is received in an electrically insulating sleeve (28) which in turn is received in a cavity formed in a metallic, high strength hexport housing so that the shield member is electrically isolated from the hexport housing.
    Type: Grant
    Filed: November 3, 2003
    Date of Patent: August 24, 2004
    Assignee: Texas Instruments Incorporated
    Inventor: Stephen P. Greene
  • Etch back of interconnect dielectrics
    Patent number: 6780756
    Abstract: An embodiment of the invention is a metal layer 14 of a back-end module 6 where the height of the interconnects 17 is greater than the height of the dielectric regions 20. Another embodiment of the invention is a method of fabricating a semiconductor wafer 4 where the height of the interconnects 17 is greater than the height of the dielectric regions 20.
    Type: Grant
    Filed: February 28, 2003
    Date of Patent: August 24, 2004
    Assignee: Texas Instruments Incorporated
    Inventors: David G. Farber, Ting Tsui, Robert Kraft, Craig Huffman
  • Vertical compensation in a moving camera
    Patent number: 6781623
    Abstract: A hand-held device comprising a housing (10) shaped and dimensioned to allow the device to be hand held, a display (12) secured to the housing for displaying moving pictures on a frame-by-frame basis, and a camera (16, 18) having an optical axis (O) extending generally away from the display to image a person who is viewing the display. The hand-held device further comprises a sensor (20) configured to determine a rotational angle between an alignment axis (V) of the hand-held device and a reference alignment axis in real space. Alternative embodiments use a reference alignment axis obtained on the basis of data content of the images, as determined by image processing techniques. In this way, subjective picture quality can be improved by compensating for vertical mis-alignment of the image content of the frames obtained by the camera.
    Type: Grant
    Filed: July 13, 2000
    Date of Patent: August 24, 2004
    Assignee: Texas Instruments Incorporated
    Inventor: David Thomas
  • Gradient dragout system in a continuous plating line
    Patent number: 6780253
    Abstract: An enhanced gradient dragout system conserves plating chemicals, including precious metals by providing a series of tanks with cascading rinse solutions having a flow rate controlled by heating the first tank to increase the evaporation rate. A portion of the concentrated solution in the heated tank is returned to the process tank. The system minimizes the requirements for clean rinse water, and the need for emptying contaminated rinse tanks with associated recovery and disposal environmental and cost issues. The low cost system is flexible and the process is adapted to the material and process requirements of the plating line.
    Type: Grant
    Filed: July 3, 2002
    Date of Patent: August 24, 2004
    Assignee: Texas Instruments Incorporated
    Inventors: Paul R. Moehle, David M. Drew, Eiman A. Hegazi
  • Method of manufacturing a semiconductor chip comprising multiple bonding pads in staggard rows on edges
    Patent number: 6780749
    Abstract: In semiconductor device 10 under this invention, bonding pads 20 are lined up in a staggered pattern on the main surface of semiconductor chip 14 which is mounted on insulated substrate 12. Multiple stud bumps are stacked on top of the pads 20a which are located on the inner rows, and these stud bumps comprise stud bump stack 28. Conductive wire 22 connects the lands 18 on the insulated substrate with the corresponding bonding pads 20. The wire is formed with its beginning at the land and its end at the bonding pad. Via the stud bump stacks 28, the ends of conductive wire 22a on the inner pads are in a higher position than the ends of conductive wires 22b on the outer pads, so that the problem of neighboring conductive wires coming into contact does not occur.
    Type: Grant
    Filed: April 16, 2003
    Date of Patent: August 24, 2004
    Assignee: Texas Instruments Incorporated
    Inventors: Kenji Masumoto, Mutsumi Masumoto, Akira Karashima
  • Method for annealing ultra-thin, high quality gate oxide layers using oxidizer/hydrogen mixtures
    Patent number: 6780719
    Abstract: An embodiment of the present invention is a method of forming an ultra-thin dielectric layer, the method comprising the steps of: providing a substrate having a semiconductor surface; forming an oxygen-containing layer on the semiconductor surface; exposing the oxygen-containing layer to a nitrogen-containing plasma to create a uniform nitrogen distribution throughout the oxygen-containing layer; and re-oxidizing and annealing the layer to stabilize the nitrogen distribution, heal plasma-induced damage, and reduce interfacial defect density. This annealing step is selected from a group of four re-oxidizing techniques: Consecutive annealing in a mixture of H2 and N2 (preferably less than 20% H2), and then a mixture of O2 and N2 (preferably less than 20% O2); annealing by a spike-like temperature rise (preferably less than 1 s at 1000 to 1150° C.
    Type: Grant
    Filed: June 20, 2001
    Date of Patent: August 24, 2004
    Assignee: Texas Instruments Incorporated
    Inventors: Hiroaki Niimi, Rajesh Khamankar, James J. Chambers, Sunil Hattangady, Antonio L. P. Rotondaro