Abstract: An amplifier architecture using actively phase-matched feed-forward linearization includes: a first signal path having a scaling amplifier 40 in series with a main amplifier 42; a second signal path having a replica amplifier 44 in series with a correction amplifier 46; and a combining node 48 that combines the first signal path and the second signal path. This topology places the scaling amplifier 40 in the main signal path. By inverting the scaling factor from &bgr; to 1/&bgr;, this topology retains the distortion cancellation property while balancing the two signal paths. In this case the scaling amplifier 40 attenuates the input signal rather than amplifying it. The end result remains the same. The main amplifier output signal is lower than the replica amplifier's by a factor of &bgr;. This results in a third-order distortion component that is &bgr;3 times bigger at the replica amplifier output.

Abstract: The present invention is directed to a fast Fourier transform (FFT) architecture. In one embodiment, the FFT architecture includes a pipeline segment having a plurality of data-independent pipelines that receive different time-domain data samples and generate therefrom corresponding intermediate results. Additionally, the FFT architecture also includes a parallel segment, coupled to all of the pipelines, that receives the corresponding intermediate results and generates therefrom corresponding frequency-domain results.

Abstract: Wireless personal area networks with frequency hopping and rotation of the frequency hopping sequences. In one embodiment, a method of wireless communication is provided, the method including: transmitting a beacon frame by a piconet coordinator that specifies a rotation index and hopping index; receiving a beacon frame by a device associated with or to be associated with the piconet coordinator; extracting the rotation index and hopping index by the MAC of the recipient device and communicating them to the PHY for transmission and reception in a current superframe; missing a subsequent beacon frame by a recipient device; and using the rotation index and hopping index previously received to determine a current frequency hopping sequence for a current superframe following the missed beacon frame.

Abstract: Transistor isolation is improved by eliminating the channeling tail of an N well implant. To do this, a low dose, high energy implant of an oppositely charged dopant ion is implanted, targeted at the depth of the channeling tail.

Abstract: The present invention provides a vertical bipolar transistor 110, a method of manufacture therefor, and an integrated circuit including the same. The vertical bipolar transistor 110 may include, in one embodiment, a second epitaxial layer 140 located over a first epitaxial layer 130, wherein the second epitaxial layer includes at least two dopant profiles 143, 147. The vertical bipolar transistor 110 may further include a collector 154, a base 156 and an emitter 158 located over or within the second epitaxial layer 140.

Abstract: A quadrature divider includes a first analog mixer (20, 30) for receiving a digital input signal at a predetermined frequency at a first input of the mixer and a second analog mixer (24, 32) for receiving the input signal with a 180° phase shift at a first input of the mixer. The output of the first mixer is coupled to a second input of the first mixer and an output of the second mixer is coupled to a second input of the second mixer.

Abstract: A symmetric glitch free clock multiplexing circuit allows the input clock to a digital or analog processing unit to be switched from one frequency to the other at any moment during the operation, assuming the respective clocks themselves are stable. There exist no restrictions on the clocks or the switch control signal to be synchronous in any fashion. This circuit guarantees a glitch free output and also prevents short cycling of the output clock. Since all the related clocks and switch control signal are asynchronous, this circuit further eliminates meta-stability problems. Its symmetrical architecture allows the circuit to function with the output clock being switched from slow clock to fast clock and vise versa.

Abstract: A power integrated circuit architecture (10) having a high side transistor (100) interposed between a control circuit (152) and a low side transistor (100) to reduce the effects of the low side transistor on the operation of the control circuit. The low side transistor has a heavily p-doped region (56) designed to reduce minority carrier lifetime and improve minority carrier collection to reduce the minority carriers from disturbing the control circuit. The low side transistor has a guardring (16) tied to an analog ground, whereby the control circuit is tied to a digital ground, such that the collection of the minority carriers into the analog ground does not disturb the operation of the control circuit. The low side transistor is comprised of multiple transistor arrays (90) partitioned by at least one deep n-type region (16), which deep n-type region forms a guardring about the respective transistor array.

Abstract: A composite lid for a semiconductor package, in which the lid includes at least two materials. The first material is disposed over and attached to the back surface of the die with a low-modulus thermal gel and the second material is disposed towards the perimeter of the lid. The second material has a modulus of elasticity greater than the modulus of elasticity of the first material, and preferably, at least twice that of the first material.

Abstract: A method and circuit for determining the accuracy of a measurement of a bit line voltage or a charge distribution for readout from FeRAM cells uses sense amplifiers to compare a bit line voltage to a series of reference voltages and then determines upper and lower limits of a range of range of reference voltages for which sensing operation provide inconsistent results. One embodiment uses an output signal of a sense amplifier to control a pull-down transistor of an I/O line and alternative precharging schemes for the I/O line allow determining both limits using the same compression circuitry to process a result value stream on the I/O line.

Abstract: MOSFET fabrication methods with high-k gate dielectrics for silicon or metal gates with gate dielectric deposition control including TXRF. TXRF permits analysis of gate (or capacitor) high-k dielectrics down to about 5 nm thickness.

Abstract: The present invention discloses a polishing pad that can facilitate process stability, extend length of use, and mitigate process non-uniformity and process induced defects for chemical mechanical planarization processes. The polishing pad of the present invention is a composite of a top pad and a sealed sub-pad. The sealed sub-pad has a sealing mechanism that mitigates liquid penetration into the sub-pad thereby maintaining a substantially uniform compressibility of the sub-pad and the polishing pad and extending a useable life of the polishing pad.

Abstract: An embodiment of the invention is a method to reduce the corrosion of copper interconnects 90 by forming a thiol ligand coating 130 on the surface of the copper interconnects 90.

Abstract: The invention relates to a software system and method for configuring a software system for interaction with a hardware system. In this method, the software system (140) is executed on a host processor interconnected with the hardware system (103). A database (152) is accessed to obtain a description of a set of functional components present within the hardware system (103). A software representation (154) of the capabilities of each functional component is created by using the description of the set of functional components. Then, the software representation (154) is interrogated to determine a set of operational capabilities of the hardware system (103). The software system (140) is then operated in a manner that is responsive to the set of operational capabilities of the hardware system (103).

Abstract: A new all digital transistor CMOS very high DC-gain amplifier (30) that uses an internal positive-feedback technique. This amplifier (30) does not require perfect matching of transistors (M2,M3) to achieve the very high DC gain. The DC gain has a very low sensitivity to the output voltage swing. An implementation of a sample and hold circuit (60) constructed using the amplifier (30) is also described. A special layout pattern (80) is used to cut the parasitic capacitance to enhance the amplifier speed.

Abstract: A port fitting is formed with a closed, pedestal end forming a diaphragm on which a strain gauge sensor is mounted. A support member is received on the pedestal end and is formed with a flat end wall having an aperture aligned with the sensor. A portion of a flexible circuit assembly is bonded to the flat end wall with a connector disposed over the support member. A tubular outer housing is fitted over the several components and its bottom portion is welded to the port fitting while its top portion places a selected load on an O-ring received about the connector as well as internal components of the transducer. In one embodiment, a loading washer (72a) is disposed over the O-ring on a first portion (70a) of a two portion connector (70) and retained by a second connector portion (70b). Protrusions (76a1) formed on the tubular housing (76) pass through cut-outs in the second connector portion to place a load on the loading washer.

Abstract: A method is described for forming a memory structure using a hardmask (65). The hardmask (65) protects the second polysilicon layer (55) during a SAS etch process. In addition, sidewall structures (95) are formed which protect the inter-polysilicon dielectric layer (45) during the hardmask (65) etch process.

Abstract: Correcting a mask pattern includes accessing a record associated with an uncorrected pattern that comprises segments. The record associates each segment with a correction grid of a number of correction grids, where each correction grid comprises points. A segment is selected, and an optimal correction for the segment is determined. A correction grid associated with the segment is determined. The segment is snapped to a subset of points of the associated correction grid, where the subset of points is proximate to the optimal correction, to form a corrected pattern of a mask pattern.

Abstract: An integrated circuit (IC) chip has a metal network of electrical power distribution lines which have a thermal conductance at least an order of magnitude greater than underlying thin film electrical interconnects. These lines are deposited on the surface of the chip (FIG. 2), located directly over active IC components, and electrically and thermally connected vertically to selected active components below the lines. Electrical conductors are operable to connect the lines to an outside source, and additional electrically non-functional conductors are distributed on the lines, operable to steepen the thermal gradient for thermal flux away from said active components and lines.

Abstract: A high PSRR, low power semiconductor digitally controlled oscillator (DCO) architecture employs only one simple current steering D/A converter directly on top of a multi-stage current controlled oscillator. The architecture provides a good building block for many circuit applications, e.g., all digital phase lock loops, direct modulation transmitters for wireless devices, and the like.