Abstract: A via etch to contact a capacitor with ferroelectric between electrodes together with dielectric on an insulating diffusion barrier includes two-step etch with F-based dielectric etch and Cl- and F-based barrier etch.

Abstract: A Class-D switching amplifier (20) having a terinary modulation scheme implemented in an H-bridge configuration. The present invention has four states of operation, and achieves increased efficiency and reduced cost by delivering current to the load only when needed, and once delivered, maintaining the current. The Class-D switching amplifier eliminates the need for post amplifier filters.

Abstract: A fluid pressure transducer assembly (10) includes an exemplary silicon or ceramic capacitive transducer (22) having a relatively flexible diaphragm portion (22e) mounted on a ceramic substrate or circuit board (18) over a bore (18a) so that the diaphragm is exposed to fluid pressure from a port (12m) received through the bore. The circuit board is received in a plastic housing (12) laterally positioned by guides (12e, 12f) on three height control pins (12d) to vertically position the circuit board a defined, precise distance above a platform (12b) on which a bead of adhesive sealing material has previously been placed, the sealing material having a height greater than the distance between a plane in which the free end of the height control pins lie and a plane in which the top surface of the platform lies. As a result, the circuit board is sealed to the plastic housing through a bead having a uniform, precise height all around its circumference to isolate temperature expansion stresses.

Abstract: An integrated circuit containing a resistor and the resistor per se. The circuit includes a substrate (2), a semiconductor resistor (3) on the substrate and a layer of electrically insulating material (5) disposed over the substrate and the semiconductor resistor having at least one contact (11, 13, 15) extending therethrough to the semiconductor resistor, the contact having an electrical path therein extending to and forming an interface with an end portion of the semiconductor resistor. The semiconductor resistor has a semiconductor resistor body, preferably of doped polysilicon, having one of a positive or negative temperature coefficient of resistance and a resistor head. The resistor head consists essentially of the electrical path which is metal interconnect, the contacts and then interface to and from the resistor body and in contact with the resistor body, the resistor head having the other of a positive or negative temperature coefficient of resistance.

Abstract: Multipoint Stations are controlled by one or more pilot tones broadcasted by a base station. The pilot tones are used to control the local oscillators of the remote stations both for receive and for transmit. The pilot tone is also used to control the input gain and the transmit gain of the remote station.

Abstract: An integrated circuit for use in a computer system having a host computer and at least one mass storage peripheral device has a controller circuit for the mass storage peripheral device for receiving information from the device and an interface circuit to interface the information from the device to the host computer via a bus mastering bus, such as a PCI bus, a 1394 bus, or the like, in the host computer. The integrated circuit is adapted to be located within the host computer and to interface to the peripheral device. The integrated circuit may include a portion of a read channel circuit, which is connected to receive information from the peripheral device. The integrated circuit may also contain other circuitry for the control and operation of the peripheral device, such as a digital signal processor, a buffer manager, a speed matching buffer, servo logic to control servo circuits to spin a motor of the peripheral device, or the like.

Abstract: A MOSFET device with buried contact structure on a semiconductor substrate has the following major elements with their relative locations. A gate insulator is on a portion of the substrate and a gate electrode is on the gate insulator. A gate sidewall structure is located on sidewalls of the gate electrode. Inside the substrate, a lightly doped source/drain region is under the gate sidewall structure, and a doped source/drain region is abutting the lightly doped source/drain region and located aside from a region under the gate sidewall structure. In addition, a doped buried contact region is also in the substrate next to the doped source/drain region. On the substrate, a silicon connection is located on a portion of the doped buried contact region, and a shielding block is on the doped buried contact region covering only a region uncovered by the silicon connection.

Abstract: A method of transferring a semiconductor die from a wafer containing a plurality of semiconductor dice. There is provided a semiconductor wafer having a top side and an opposing bottom side and a plurality of dice formed therein, each die containing a portion of the top side and the opposing bottom side. The wafer is removably secured to a support and the wafer is operated upon to form individual dice on the support. The support is preferably a flexible film. A tool is disposed between the support and the bottom side of a the die by creating a vacuum between the tool and the bottom side to cause adherence of the die to the tool and the die is removed from the support with the tool and placed in a die carrier with the top side facing the carrier and the vacuum is then released. The film, when flexible, is stretched to separate the dice from each other and create streets between adjacent dice so that the tool can be disposed under the die from the street.

Abstract: End cap apparatus (2) is received in the open end of an electrochemical cell casing (6) and is particularly adapted to be crimped thereto electrically separated from the casing by a gasket (4). The end cap apparatus incorporates current interrupt safety protection features including high rate overcharge protection through an over-temperature and/or low pressure switch (22, 12d-18, 18′, 18″, 118a), low rate overcharge and overdischarge protection through a low pressure switch (12d-18, 18′, 18″, 118a), extended short circuit protection through an over-temperature switch driven by l2r heating of internal components (20, 22, 16, 12, 12′, 16′, 16″, 16′″, 12v, 102, 122, 120), and pressure venting through a frangible portion (12e) of a diaphragm. The diaphragm can be integrally formed with a header (12, 12″, 12′″, 12iv) or can be a separate element (32, 82, 92, 108, 112, 112′ 112″, 112′″).

Abstract: A method for generating an updated path metric includes combining each of first and second provisional path metric first portions with an associated branch metric first portion to produce a first provisional updated path metric first portion candidate and a second provisional updated path metric first portion candidate, respectively. The method also includes selecting one of the provisional first portion updated path metric candidates to produce an updated path metric first portion candidate and combining any carry component of the selected updated path metric first portion candidate with a path metric second portion and a branch metric second portion to produce a first updated path metric second portion candidate. The method also includes comparing the updated path metric second portion candidate to at least one other updated path metric second portion candidate; and selecting one of the updated path metric second portion candidates to produce an updated path metric second portion.

Abstract: This invention proposes a process to form planarized twin-wells for CMOS devices. After depositing pad oxide and a silicon nitride layers, a high-energy phosphorus ion implantation is performed to form the N-well by using a photoresist as a mask. A thick oxide layer deposited by liquid phase deposition process is then grown on the N-well region part of the silicon nitride layer, but not on the photoresist. After stripping the photoresist, a high-energy boron ion implantation is carried out to form the P-well by using the LPD-oxide layer as a mask. The thick LPD-oxide layer is removed by BOE or HF solution. Trenched isolation regions are formed to isolate and define active regions. After removing the pad oxide and the silicon nitride layer, the CMOS device is fabricated by standard processes.

Abstract: A data processing system (15) including a synchronous random access memory (30) and a method for accessing the synchronous random access memory are disclosed. A digital processor (20) of the data processing system is coupled to with a system clock circuit (65) that produces a system clock signal for controlling operation of the digital processor. Addressable storage cells within the synchronous random access memory are accessed in response to the system clock signal and an address select signal (ADS) to write data into the storage cells or read data out from the storage cells. Initial row and column addresses are latched into a row address buffer (48) and a column address buffer (49). A number of data bits corresponding to a control signal such as a wrap length (WL) signal are read out from the memory in synchronization with the system clock signal. The synchronous random access memory device may be fabricated as a dynamic storage device or as a static storage device.

Abstract: An adherent hardmask structure and method of etching a bottom electrode in memory device capacitor structures that dispenses with the need for any adhesion promoter during the etching of the bottom electrode. By using silicon nitride as a hardmask 220, the processing is simplified and a more robust capacitor structure can be produced. Silicon nitride 220 has been shown to yield significantly enhanced adhesion to platinum 210, as compared to silicon oxide formed by any method. Since silicon nitride 220 is oxidation resistant, it advantageously resists any oxygen plasma that might be used in the etch chemistry. This etching process can be used during processing of high-k capacitor structures in DRAMs in the ≧256 Mbit generations.

Abstract: A test circuit (10) is provided to enable testing for faults in internal cascode transistors Q2 and Q3, which form part of, for example, a level shifting circuit. Test circuit (10) is comprised of test transistors Q6 and Q7 connected to regulating transistors Q5 and Q8. When Q2 and Q3 are functioning properly, no current flow through test circuit (10). If, however, either or both of Q2 or Q3 has a drain to source short, current flows through test circuit (10) thus providing an indication of the fault.

Abstract: A circuit for ensuring stabilized configuration information upon power-up is disclosed. In one embodiment, a semiconductor device includes a configuration information stored in a number of nonvolatile storage elements (fuse bits (16)). A configuration power-on reset circuit (10) generates a signal for latching the configuration data into volatile configuration registers (18) on power-up. The configuration data signals are generated in response to a power-on reset (POR) pulse, and not latched until a predetermined delay after the POR pulse is terminated. The predetermined delay allows time for the data signals from the fuse bits (16) to “settle.” Subsequent POR pulses will not result in another latching action.

Abstract: A method for fabricating a high speed and high density nonvolatile memory cell is disclosed. First, a semiconductor substrate with defined field oxide and active region is prepared. A stacked silicon oxide/silicon nitride layer is deposited and then the tunnel oxide region is defined. A thick thermal oxide is grown on the non-tunnel region. After removing the masking silicon nitride layer, the source and drain are formed by an ion implantation and a thermal annealing. The pad oxide film is etched back, and a metal silicide film is formed and then stripped. A topography of the doped substrate region is then made rugged. Thereafter, a thin oxide is grown on the rugged doped substrate region to form a rugged tunnel oxide. Finally, the floating gate, the interpoly dielectric, and the control gate are sequentially formed, and the memory cell is finished.

Abstract: In one embodiment, there is a single integrated circuit microprocessor (10). The microprocessor has an instruction pipeline (12) which comprises an execution stage (12a) operable to process an information unit of a first length. The microprocessor further includes a cache circuit (20) comprising a memory (34) operable to store a transfer unit of information of a second length and accessible by the instruction pipeline. The second length corresponding to the capability of the cache circuit is greater than the first length corresponding to the execution stage operability. Lastly, the microprocessor includes a block move circuit (24) coupled to the cache circuit and operable to read/write a transfer unit of information of the first length into the memory of the cache circuit.

Abstract: A method for shuffling capacitors from period to sample period in a stage of a multi-stage analog to digital converter (“ADC”). The ADC stage includes a plurality of capacitors usable for storage of charge during a sample phase and for providing during an amplification phase, in conjunction with an amplifier, an output signal having a voltage representing the difference between the digital output voltage level for the stage and the analog input voltage level for the stage. The method includes the following steps. First, the input is provided to the plurality of capacitors during the sample phase to capture and hold the first analog voltage level at a first time in the sample phase.

Abstract: A RESURF LDMOS transistor (32) has a drain region including a first region (24) and a deep drain buffer region (34) surrounding the first region. The first region is more heavily doped than the deep drain buffer region. The deep drain buffer region improves the robustness of the transistor.

Abstract: A hard disk drive system (10) includes a rotating magnetic disk (13), an arm (16) moved by a voice coil motor (18), and a read/write head (21) movably supported on the arm by a microactuator (22). The read/write head is moved approximately radially of the disk in response to operation of the microactuator or movement of the arm. The microactuator has a nonlinear transfer function. A control system (62) for controlling the microactuator and the voice coil motor includes a control technique (126) having a nonlinear transfer function which is substantially an inverse of the nonlinear transfer function of the microactuator. Control of the microactuator is effected through the control technique, the control technique linearizing the control of the microactuator.