Abstract: A single chip dual function 10 Base-T/100 Base-X physical layer interface device (PHY) compatible with existing 5 V parts is provided. The PHY includes a media-independent interface (MII) and connects to an unshielded twisted pair cable via an isolation transformer and a single RJ45 connector. The PHY includes built-in auto-negotiation circuitry that allows for automatic selection of half/full duplex 10 Base-T and 100 Base-TX, while auto-polarity correction circuitry ensures immunity to receive pair reversal in the 10 Base-T mode of operation. The PHY includes internal PLL circuitry that uses a single 20 MHz clock or crystal, but that is suitable for either speed mode. The PHY includes low-power and power down modes. The 10 Base-T portions of the PHY include smart squelch for improved receive noise immunity. The PHY includes high jitter tolerance clock recovery circuitry and transmit jabber detection circuitry. The 10 Base-T portions of the PHY include on board transmit waveshaping.

Abstract: In order to form an isolation structure in a substrate, a blocking layer (13, 14) is fabricated over the substrate (12), after which portions of the blocking layer and the substrate are removed at an isolation region (22). A dielectric layer (26) is then deposited over the blocking layer and the isolation region. Thereafter, a chemical-mechanical polishing process is carried out on the dielectric layer, so as to remove a substantial portion of the dielectric layer disposed above an upper surface of the blocking layer. A non-patterned etch is then carried out on the dielectric layer, in order to remove a remaining portion of the dielectric layer disposed above the upper surface of the blocking layer.

Abstract: An apparatus for the fabrication of a semiconductor assembly and a method of underfilling flip-chip devices are disclosed. The apparatus for multiple controlled dispensing of polymeric precursors filled with silica and anhydrides comprises a center feed tube supplying the proecursor; a header connecting the center tube to a plurality of distribution tubes, whereby the distribution tubes acquire predetermined distances from the center tube; a nozzle at the end of each distribution tube; and these nozzles having increasingly larger cross sections, the farther the respective distribution tube is positioned from the center tube, whereby the dispense rate of the precursor remains the same for all distribution tubes.

Abstract: Partial wafer processing is achieved by down loading the wafer map of the whole wafer from a host (2) and if the partial wafer (half or quarter) contains the reference die (4) move table to a locator die (5) and upload locator die coordinates to wafer map data host (6) and remove other half or quadrants die coordinates from the map (10). If the partial wafer is not in the first half or first quadrant position wafertable to auxiliary reference die, find out which half or quadrant partial wafer belongs (8) and compute auxiliary reference die coordinates from locator die coordinates (9) and then using auxiliary die coordinates as information remove other quadrant or half die coordinates from the map (10).

Abstract: An electronic device is provided that compromises a dielectric layer (12) disposed outwardly from a substrate (10). The dielectric layer (12) has at least one contact opening (14) formed through the dielectric layer (12). The device has an adhesion layer (16) disposed outwardly from the exposed surfaces of the dielectric layer (12) and the substrate (10). A first barrier layer (18) is formed outwardly from the adhesion layer (16). A second barrier layer (20) is formed outwardly from the first barrier layer (18). A conductive plug (24) fills the contact opening (14) and is disposed outwardly from the second barrier layer (20).

Abstract: Apparatus for generating and displaying data on a monitor 28 such as a CRT of LCD display. The display is comprised of a plurality of images, each located at positions on the face of the monitor defined by multi-digit coordinate values in a multi-coordinate system. Units of data are stored in linear display memory 26, each such unit of data corresponding to and defining the image to be displayed at one of said positions. The apparatus includes a circuit 60 which places selected bits of said multi-digit coordinate values in a preselected order to define the address or offset in said linear display memory at which is located the corresponding unit of data.

Abstract: A internal circuitry protection scheme which protects on-IC circuitry when an external pin is shorted to a higher than normal voltage. The disclosed solution eliminates cross-talk due to a parasitic NPN.

Abstract: The invention relates to switching regulators with at least one inductance and four controllable switches which can be controlled by a control circuit in such a way that the switching regulators may be operated separately in a step-up mode as well as in a step-down mode, whereby in each clock cycle of either of the modes only two switches each are actuated, which in comparison with previous similar switching regulators, where in each clock cycle four switching operations take place, results in current saving effects because of reduced switching losses and lower currents. These are achieved by an element which constantly monitors the duty cycle of one of the switches and, when in the step-down mode the duty cycle approaches 100%, causes a switch-over into the step-up mode, and when in the step-up mode the duty cycle of 0% is approached, causes the switch-over into the step-down mode. Furthermore, the invention relates to methods for operating switching regulators.

Abstract: A method of forming a semiconductor device includes separating a semiconductor gate body from the outer surface of the substrate by a gate insulator layer, forming a conductive drain region in the outer surface of the substrate and spaced apart from the gate conductor body, and forming a conductive source region in the outer surface of the substrate and spaced apart from the gate conductor body opposite the conductive drain region to define a channel region in the substrate disposed inwardly from the gate body and the gate insulator layer. The method also includes depositing a metal buffer layer over the conductive source region and conductive drain region, depositing a metal layer over the metal buffer layer, and reacting the metal layer and metal buffer layer with the conductive source region and conductive drain region to form respective first and second silicide regions.

Abstract: A microprocessor (12) comprising a memory system (20) for outputting data in response to an address, wherein the memory system is further operable to receive a prefetch request having a predicted target data address. The microprocessor further includes a load target circuit (56 or 112), which comprises a first plurality of entries (116) of a first length and a second plurality of entries (114) of a second length. Each of the first plurality of entries comprises a value (ADDRESS TAG) for corresponding the entry to a corresponding first plurality of data fetching instructions. Further, each of the first plurality of entries further comprises a value (POINTER A) for indicating a corresponding predicted target data address. Each of the second plurality of entries also comprises a value (ADDRESS TAG) for corresponding each of the second plurality of entries to a corresponding second plurality of data fetching instructions.

Abstract: An educational toy (10) having a dodecahedron shape is formed with a different visual display on each planar face (17-28). A position sensing mechanism (50) is oriented inside the toy (10) to inform a microprocessor (62) which one of the planar faces (17-28) is in the “up” position. As the toy (10) is turned or moved a signal is generated to “power on” and a musical tune is played. When one of the planar faces (17-28) is stopped in the “up” position, the position sensing mechanism (50) informs the microprocessor (62) and an aural response corresponding to the visual display is transmitted through a speaker (44). If the toy (10) is left alone for a specified period of time, a warning tune is transmitted. If the toy (10) is still not moved thereafter, the toy (10) will automatically “power off”.

Abstract: A method and device for producing an accurate approximation of a digital input word translated by a monotonic transfer function. The digital word is translated into a non-monotonic output word comprised of a closest-approximation component and an error component. The error component is zero for regions in which each consecutive input word produces a unique closest-approximation component. In regions in which each consecutive input word produces the same closest-approximation component, the error signal represents the number of consecutive input words which produce the same closest-approximation component, and the position within that run of consecutive input words occupied by the present input word.

Abstract: A plasma process is described which produces an undamaged and uncontaminated silicon surface by consuming silicon by continuous oxidation through a surface oxide layer and a simultaneous etch of the exposed silicon oxide surface. The surface silicon dioxide layer thickness is controlled as an equilibrium between oxide growth from oxygen atoms reaching the silicon surface and etching of the oxide surface. The silicon dioxide protects the silicon surface from plasma damage and from contamination.

Abstract: Pulsed plasma deposition of polymers as dielectrics for integrated circuit interconnects fills minimal gaps and yields a porous polymer with thermal stability by plasma off times sufficiently long to dissipate plasma on time energy input plus an anneal of the deposited polymer to drive off occluded monomers and small oligomers.

Abstract: A method of laying out traces for connection of bond pads of a semiconductor chip to a printed wiring board or the like and the layout. There is provided a substrate having top and bottom surfaces with a plurality of rows and columns of vias extending therethrough from the top surface to the bottom surface and having a solder ball secured at the bottom surface to each via. A plurality of pairs of traces is provided on the top surface, each trace of each pair of traces extending to a different one of the vias and extending to vias on a plurality of the rows and columns, each of the traces of each pair being spaced from the other trace by a ball pitch, being maximized for identity in length and being maximized for parallelism and spacing. Each of the traces of a pair is preferably be further maximized for identity in cross-sectional geometry. A differential signal pair is preferably applied to at least one of a pair of traces.

Abstract: Generally, and in one form of the invention, an integrated circuit is disclosed for providing low-noise and high-power microwave operation comprising: an epitaxial material structure comprising a substrate 10, a low-noise channel layer 14, a low-noise buffer layer 16, a power channel layer 18, and a moderately doped wide bandgap layer 20; a first active region 24 comprising a first source contact 32 above the wide bandgap layer 22, a first drain contact 36 above the wide bandgap layer 22, wherein the first source contact 32 and the first drain contact 36 are alloyed and thereby driven into the material structure to make contact with the low-noise channel layer 14, and a first gate contact 28 to the low-noise buffer layer 16; and a second active region 26 comprising a second source contact 34 above the wide bandgap layer 22, a second drain contact 38 above the wide bandgap layer 22, wherein the second source contact 34 and the second drain contact 38 are alloyed and thereby driven into the material structure t

Abstract: A wire bonding method includes aligning the face of a capillary along a first direction to make a first wire bond at a first bond point. The capillary face is realigned to a second direction to make a second wire bond at a second bond point. The realignment may be achieved by a system including an wire bonding capillary having an indicator located thereon. A detector detects a signal from the indicator. The signal corresponds to a rotational alignment of the capillary and, therefore, to a direction of alignment of the capillary face. A first signal indicates a first alignment of the capillary face and a second signal indicates a second alignment of the capillary face. The signals may each have a relative signal strength which indicates rotational an offset of the capillary face from a given direction.

Abstract: A content addressable memory (CAM) (30) and a method of using it to sequentially match tags stored in the CAM to a target tag. The CAM (30) has a tag memory (20) comprised of tag cells (10, 10a) and also has a data cache. Each tag cell (10, 10a) is structured like a conventional RAM cell for storing a bit of data but also has a multiplexing switch (16) at its output. The multiplexing switch (16) applies a signal representing the tag cell's contents to a readline (15). A tag compare circuit (25) external to tag memory (20). On each readline, tag compare circuit (25) compares a bit from each cell (10, 10a) in a selected column to a bit of the target address. This cycle is repeated for all bits of the target address and successive columns of the tag memory unless terminated by a mismatch for all cells (10, 10a) in a column. The tag compare circuit (25) has logic circuitry that maintains a “hit” output signal.

Abstract: An architecture for a high-capacity high-speed synchronous dynamic random access memory (SRAM) (400) is disclosed. The SDRAM (400) includes memory cells logically arranged into a number of array banks (402a-402d). The array banks (402a-402d) each include first sub-banks (404a-404d) situated toward a first end of the SDRAM and second sub-banks (406a-406d) situated toward a second, opposing end of the SDRAM (400). Sub-bank buses (420a-420h), each of which includes a number of data I/O lines, couple each of the first sub-banks (404a-404d) to a first I/O circuit (412) situated toward the first end of the device, and couple each of the second sub-banks (406a-406d) to a second I/O circuit (414) situated toward the second end of the device. In this manner, overlap of the sub-bank buses (420a-420h) is limited toward the first and second ends of the device, eliminating the need to run data I/O lines across the device, and thus preventing a data I/O line routing bottleneck in the central portion of the SDRAM (400).

Abstract: The invention provides a low inductance semiconductor package for RF circuits having a flat leadframe with internal leads formed upward to be in very close proximity to the die mount pad. The die mount pad is exposed through the package backside and serves both as a ground plane and as a heat spreader. The external leads are flat and extend beyond the package edge so that good solder connections to a printed wiring board can be made and inspected. The lead tips exposed beyond the package further provide a position for mold clamping and for test probing the device.