Abstract: An integrated circuit (13) includes a P-epi substrate (51) having first and second n+ isolation layers (53, 54) buried therein, the first and second isolation layers being respectively coupled to ground and to a supply voltage (VCC). A contact region (52) of the substrate is closely adjacent a first isolation layer, is spaced from the second isolation layer, and is coupled to ground. First and second P-epi portions (57, 58) of the substrate are disposed within the first and second isolation layers. The first portion includes an n+ source region (62) disposed in a p-well (61) which is closely adjacent the first isolation layer in the vicinity of the contact region, and includes an n+ drain region (68). The second portion includes an n+ source region (77) coupled to the drain region in the first portion, and an n+ drain region (82) coupled to the supply voltage.

Abstract: The purpose of the present invention is to reduce the warpage of the semiconductor package caused by thermal contraction. According to the present invention, semiconductor device (9) has plate-shaped member (7) which is positioned on a surface of semiconductor chip (1) and is sealed together with semiconductor chip (1) with molding resin (8). Said plate-shaped member (7) has a linear expansion coefficient that is less than the linear expansion coefficient of the aforementioned molding resin. By placing a plate-shaped member with a small linear expansion coefficient on semiconductor chip (1), it is possible to reduce the thermal contraction on the upper side of the semiconductor chip. Also, the presence of the plate-shaped member on the semiconductor chip leads to substantial reduction in the thickness of the molding resin on the semiconductor chip. The pulling force due to contraction of the molding resin that leads to warping is proportional to the thickness of the molding resin.

Abstract: A transport stream parser system is provided that utilizes an intermediate buffer for containing packets after processing with an associated flag and then use a processor for further processing of packets selected by such flags.

Abstract: A ferroelectric structure on an integrated circuit is disclosed, which may be used, for instance, in a high-speed, non-volatile, non-destructive readout random-access memory device. Generally, the ferroelectric structure combines a thin film ferroelectric variable resistor and a substrate (e.g. silicon) transistor, using a semiconducting film which is common to both. A field effect transistor 26 integrated into substrate 30 has a gate oxide 36 and a semiconducting gate electrode 38 with electrical connections at a first end 44 and a second end 46. Overlying gate electrode 38 is a ferroelectric thin film 40 and a conductive electrode 42. The polarization of ferroelectric thin film 40 is set by applying an appropriate voltage between gate electrode 38 and conductive electrode 42.

Abstract: A method of operating a microprocessor. The method issues (52) a first address to a tag memory (18). This first address is set to a state to address a row in an information memory corresponding to the tag memory. The method also determines (58) whether the row in the information memory to be addressed by the first address is defective. In response to determining that the row in the information memory to be addressed by the first address is defective, the method performs two steps. First, it converts (60) the first address to a second address different than the first address. Second, the method addresses (66) the information memory with the second address in response to detecting a hit in the tag memory. Alternatively, if the method determines that the row in the information memory to be addressed by the first address is not defective, it instead addresses the information memory with the first address in response to detecting a hit in the tag memory.

Abstract: A digital self calibration scheme for pipelined AD converters. The scheme can correct for capacitor mismatch, capacitor non-linearity, amplifier gain and amplifier non-linearity.

Abstract: An integrated circuit carries an intellectual property core. The intellectual property core includes a test access port 39 with test data input leads 15, test data output leads 13, control leads 17 and an external register present, ERP lead 37. A scan register 25 encompasses the intellectual property core and ERP lead 37 carries a signal indicating the presence of the scan register.

Abstract: A digital to analog converter (“DAC”) (20). The DAC includes an input (23) for receiving a plurality of successive digital words (D3−D0), and circuitry (28, 30) for storing the plurality of successive digital words. The DAC also includes a string (12′) of series connected resistive elements, wherein the string comprises a plurality of voltage taps (T0′-T15′). The DAC further includes an output (OUTA) for providing an analog output voltage corresponding to a selected one of the plurality of successive digital words. The DAC further includes comparison circuitry (32) for comparing the selected one and an earlier received one of the plurality of successive digital words. Finally, the DAC includes circuitry (34, 24, 26) for generating the analog output voltage in response to the comparison circuitry.

Abstract: A method of fabricating a semiconductor device wherein there is provided a semiconductor substrate, preferably of silicon, having a gate insulator thereover, preferably of silicon dioxide, forming a junction, preferably a silicon/silicon dioxide interface, and a gate electrode, preferably of doped polysilicon, over the partially fabricated device. Deuterium is implanted into the structure and the deuterium is caused to diffuse through the deivce. The device fabrication is then completed.

Abstract: A low cost, microprocessor (U1) based motor controller (10) for driving a half-wave, multiple speed, reversible, DC brushless motor (30) directly from standard AC 50/60 Hz power. A large number of different speed and rotation direction combinations may be chosen before or after the motor is installed using configuration resistors (Rcol1, Rrow1). SIDACs (TS2, TS3) each serially connected to a diode (D6, D5) are connected across respective coils (COIL—1, COIL—2) to clamp the flyback energy in the windings to a few volts when triggered and allow Vemf to float when not triggered. The control adjusts the relative phase timing of commutation during start-up and during running to enhance efficiency. Locked rotor protection is provided by limiting start-up time to a selected period which is followed by a selected cool-off time.

Abstract: A packed data structure processor (25) is disclosed. The packed data structure processor (25) includes a register file (24) of multiple registers (REG0 through REG31), each of which is connected to an input of each of a plurality of operand multiplexers (26). Each operand multiplexer (26) is associated with a shift/mask circuit (28), which permits the selection of a particular portion (e.g., BYIE, WORD, DWORD) of the contents of a selected register file, for use as an operand. An arithmetic logic unit (ALU) (30) performs data processing operations upon the operands, and presents results on writeback bus (WBBUS), to external memory (18) over a memory interface (37), or to a register file (42) associated with other circuitry (44) over a coprocessor interface (41). A destination selector (40) is capable of writing to only a selected portion of a selected register, thus permitting a packed data structure to be present within the register file (24).

Abstract: A method of processing wafers containing a gate oxide assembly (10) is disclosed that reduces gate oxide damage during wafer production due to damage caused by charging. The method comprises creating an oxide gate assembly (10) on a silicon layer (11) in a production line chamber followed by the deposition of a polysilicon layer (22). Following the creation of the gate oxide assembly (10) a pressure of at least 1.2 Torr is maintained while lowering the power within the production line chamber. The invention can be used with a gate oxide layer (16) of less than 1000 angstroms.

Abstract: A pipeline analog-to-digital conversion system (10) includes a plurality of cascaded subconverter stages (12) and a digital correction unit (16). Each subconverter stage (12) includes an n-bit analog-to-digital converter (26), an n-bit digital-to-analog converter (28), and an arithmetic unit (32). The n-bit analog-to-digital converter (26) generates a second intermediate digital signal (18) as a function of a first input analog signal (24) and a corresponding first intermediate digital signal (18) received from a previous stage (12).

Abstract: A transistor is formed on the substrate (10) with a graded doping profile for the gate electrode (22). This graded profile is performed for an N-channel transistor by depositing the gate electrode with two separate layers of material. The first layer is a thin layer of N-doped poly, whereas the second layer is a layer of P-doped poly (18). A layer of cap oxide (20) is disposed over the gate electrode (22) to prevent further implantation of impurities during the source/drain implant operation.

Abstract: A data processing system (15) including a synchronous random access memory (30) and a method for accessing the synchronous random access memory are disclosed. A digital processor (20) of the data processing system is arranged with a system clock circuit (65) that produces a system clock signal for controlling operation of the digital processor. Addressable storage cells within the synchronous random access memory are accessed in response to the system clock signal and a single select signal such as an address select signal (ADS) to write data into the storage cells or read data out from the storage cells. The synchronous random access memory device may be fabricated as a dynamic storage device or as a static storage device.

Abstract: A DC to DC converter includes multiple stages to share power handling. The stages are connected in parallel paths between the source input and the load output of the power converter. An analog error signal is generated by comparing the load output signal to a reference signal. The error signal is fed to a phase shifting input of a phase lock loop. The phase lock loop is connected to receive a reference clock signal and maintain a relative clock signal shifted in phase from the reference clock signal by an amount depending on the error signal. Digital divider circuits and digital logic circuits are used to produce phase shifted variable pulse width control signals for the stages. The parallel connected power conversion stages equally share the transfer of power from the input source to an output load. A single analog to digital conversion of a single analog error signal to multiple, phase shifted, variable duty cycle clocks is provided.

Abstract: An integrated heat pump and electrical heat control (12) has thermostat signal inputs (O, W1, W2, G, Y) along with a defrost sensor input (DF_IN). The defrost sensor (22) is located in an outdoor unit (4) which also includes a compressor contactor (CC), condenser fan (16) and reversing valve (18) relays (K4, K3, K2) controlled by micro-controller (U1). The normally closed condenser fan relay (K3) is energized through the defrost sensor forming a hardware lock-out in which the defrost sensor contacts must be closed for relay (K3) to be actuated de-energizing the condenser fan. The compressor contactor (CC) is energized through a low pressure switch (24) and high pressure switch (26) forming another hardware interlock. The evaporator fan is energized by relay (K1) controlled by micro-controller (U1) and matched to the compressor for improved efficiency and comfort.

Abstract: A packaged semiconductor device and a method for burn-in and testing are disclosed. The package comprises a carrier having a pattern of contact pads for electrical connection, and also a pattern of testing pads for electrical characterization such that their location, size and composition allows a conversion to contact pads after the device has been electrically characterized following burn-in. Furthermore, an adapter and a method for burn-in and testing are disclosed for use in testing a variety of different semiconductor devices. The adapter comprises a carrier having a pattern of testing pads bordering the carrier outline, and routing strips which are structured such that the carrier is adaptable to the package of the device being tested.

Abstract: A base cell, having four sites, for use in a gate array retains the same design rules as a prior art base cell, but the area of the base cell has been reduced. The reduction in the size of the base cell is the result of arranging all transistor pairs to be fabricated over a common moat regions, thereby eliminating areas previously used for moat-to-moat spacing. In addition, at least one moat region is configured to permit a conducting path passing nearby to observe the design rules without appreciable. Components forming the base cell have been rearranged to permit the D-type flip-flop circuit to be implemented using three of the base cell sites instead of the four base cell sites required by the prior art. This component rearrangement is useful for other circuits implemented by the base cell as well.

Abstract: A video decoder circuit is provided with automatic AGC bias voltage calibration. The video decoder circuit has an input for receiving a video signal that is capacitively coupled to an analog front-end circuit. The decoder circuit includes a microprocessor-based control circuit coupled to the analog front-end circuit. The control circuit includes a bias circuit, a gain interface circuit for changing the amplitude of the video signal prior to filtering in a filter circuit, an offset circuit for changing the DC-level shift of the video signal, and a switching circuit for switching into a calibration mode by bypassing the filter circuit and connecting the gain interface circuit directly to an analog-to-digital conversion circuit of the analog front-end circuit.