Abstract: An apparatus is employed for providing for efficient communication between high level and low level processing engines in a disk formatter for formatting a disk, the high-level engine outputting at least one instruction to control disk operations to the low-level engine which processes the instruction. The apparatus includes an instruction queue within the low-level engine. The instruction queue stores the instruction received by the low level processing engine from the high level processing engine, which outputs the instruction to the memory in accordance with a first clock signal generated by the high-level engine. The instruction queue outputs the instruction in accordance with a second clock signal of the low level processing engine which corresponds to a predetermined disk transfer rate. In accordance with another embodiment of the present invention, a method is also employed for providing for efficient communication between high and low level processing engines in a disk formatter for formatting a disk.

Abstract: A packaged semiconductor device and a method for burn-in and testing are disclosed. The package comprises a carrier having a pattern of contact pads for electrical connection, and also a pattern of testing pads for electrical characterization such that their location, size and composition allows a conversion to contact pads after the device has been electrically characterized following burn-in. Furthermore, an adapter and a method for burn-in and testing are disclosed for use in testing a variety of different semiconductor devices. The adapter comprises a carrier having a pattern of testing pads bordering the carrier outline, and routing strips which are structured such that the carrier is adaptable to the package of the device being tested.

Abstract: An audiovisual communications configuration comprising an interface (28) for receiving from a computer (10) a video signal output by video circuitry (15) of the computer. In this context, the video signal is output by the video circuitry of the computer for displaying an image on a first screen display (18), and the computer includes a microprocessor (15). The audiovisual communications configuration further includes circuitry (64, 66, 68, 70) for coupling a video data signal to a telephone line (40). This circuitry for coupling a video data signal is controllable independently from the microprocessor. The video data signal is representative of the video signal output by the video circuitry. Moreover, the video data signal is configured to be received from the telephone line and decoded to display an image on a second screen display (42) remote from the first screen display. Lastly, the image on the second screen display is representative of the image on the first screen display.

Abstract: A method of processing wafers containing a gate oxide assembly (10) is disclosed that reduces gate oxide damage during wafer production due to damage caused by charging. The method comprises creating an oxide gate assembly (10) on a silicon layer (11) in a production line chamber followed by the deposition of a polysilicon layer (22). Following the creation of the gate oxide assembly (10) a pressure of at least 1.2 Torr is maintained while lowering the power within the production line chamber. The invention can be used with a gate oxide layer (16) of less than 1000 angstroms.

Abstract: A wireless data platform (10) comprises a plurality of processors (12, 16). Channels of communication are set up between processors such that they may communicate information as tasks are performed. A dynamic cross compiler (80) executed on one processor compiles code into native processing code for another processor. A dynamic cross linker (82) links the compiled code for other processor. Native code may also be downloaded to the platform through use of a JAVA Bean (90) (or other language type) which encapsulates the native code. The JAVA Bean can be encrypted and digitally signed for security purposes.

Abstract: A method of manufacturing integrated circuits uses an architecture having multiple processors and multiple memories, such that there is at least first and second groups of processors and memories. The first group has at least a first processor and at least a first memory. The second group has at least a second processor and at least a second memory. Regardless of where the architecture is sliced, the integrated circuits have a majority of the same address and data pin-outs.

Abstract: A network of electronic devices such as computers (50) and/or calculators (36, 38) uses low power communication to transmit wireless signals through a distributed antenna system (40). The distributed antenna system may be formed in conjunction with ceiling or floor tiles 62 or modular office components (44 and 46) or student desks. The distributed antenna system 40 reduces the effective distance between a transmitting and receiving device to a nominal distance.

Abstract: A synchronous memory (30), comprising a row address circuit (48,50) latches a row address signal in response to a system clock signal and a binary select signal. The row address circuit produces at least one row select signal. A column address circuit (49,51-54) latches an initial column address signal in response to the system clock signal and the binary select signal. The column address circuit produces a plurality of column select signals in synchronization with the system clock signal. A memory array (75) is arranged in rows and columns of memory cells. Each memory cell stores a respective data bit. The memory array simultaneously produces an integral multiple of M data bits in response to the row select signal and the plurality of column select signals. An output circuit (OMUX) is coupled to receive the system clock signal and the integral multiple of M data bits.

Abstract: An integrated circuit utilizing copper wiring has copper bond pads which are covered with a passivation layer to prevent unwanted reactions of the copper with metals which are bonded to it. The passivation layer can be an intermetallic of copper and titanium or a stacked layer of CuTix/TiN. Various nitrides can also be used, such as tungsten nitride, tantalum nitride, titanium silicon nitride, tungsten silicon nitride, and tantalum silicon nitride.

Abstract: A method for forming a sum of the absolute value of the difference between each pair of numbers of respective first and second sets of numbers. The method includes forming the difference between a first number of the first set and a second number of the second set. Next this difference is either added to or subtracted from a running sum based upon the sign of this difference. This is repeated until all number pairs are either added to or subtracted from the running sum of absolute values of the differences. The initial subtraction is used to set a status bit in a flag register (211) based upon a less than zero output or the carry-out. The status bit controls whether the difference is added to or subtracted from the running sum. The conditional addition to or subtraction from the running sum may generate a carry-out representing the most significant bit of the running sum. This carry-out is stored and later added to the running sum to recover the most significant overflow bits.

Abstract: A method of initializing the operation of a remote modem (10) and central office modem (20k) for asymmetric subscriber line modem communications over a twisted pair wire facility (TWP), using discrete multi-tone technology, is disclosed. The initialization process begins with the remote modem (10) issuing an initialization request, in response to which the central office modem (20k) issues an acknowledgment. The remote modem (10) includes a low-cost analog filter (21) for separating upstream communication echoes from downstream data. This analog filter (21) increases the duration of impulse response over the channel, and thus requires time-domain equalization (TEQ) process (31) performed by the remote modem (10) to filter relatively long circular prefixes, so that intersymbol interference is eliminated.

Abstract: A resonant tunneling diode (400) made of a quantum well (406) with tunneling barriers (404, 408) made of two different materials such as calcium fluoride (408) and silicon dioxide (404). The calcium fluoride provides lattice match between the emitter (410) and the quantum well (406). Further resonant tunneling diodes with silicon lattice match barriers may be made of III-V compounds containing nitrogen.

Abstract: Post-etch treatment of an etch-damaged semiconductor device includes forming a protective cover (48, 148) over an oxidizable section (18, 118) of the semiconductor device. The protective cover (48, 148) is operable to at least inhibit oxidation of the oxidizable section (18, 118). While the oxidizable section (18, 118) is covered, an oxide structure (52, 152) is formed. The oxide structure (52, 152) is operable to at least ameliorate etch damage to the semiconductor device.

Abstract: An integrated circuit includes a substrate (12) having a conductive region (18), and includes a dielectric layer (19) disposed over the substrate. An upwardly tapering frustoconical opening (22) is created through the dielectric layer to the conductive region. A barrier layer (31) is then applied, after which a thin metal layer (32) is applied, the upper end of the opening being pinched off or closed by the metal layer. Heat and pressure are then simultaneously applied, so that the metal layer flows to completely fill the available space within the opening. Selected portions of the metal layer external to the opening are then etched away. A further dielectric layer (41) is applied over the barrier layer and metal layer, and then planarization is carried out on the further dielectric layer.

Abstract: A method of optimizing a computer program for reduced power consumption by a processor (10) having functional units (11d, 11e) that are independently controllable by instructions. The processor's instruction set (FIG. 4) has instructions that may be directed to a particular functional unit (11d, 11e) so as to place that functional unit in a power-down state while not being used during a program segment.

Abstract: For reading the data stored in a transponder by means of an interrogation device, the interrogation device at first receives the background noise for the purpose of detecting interference frequencies present in this background noise. On the basis of the interference frequencies acquired, coefficients for an adaptive filter are computed by means of which this filter may be tuned in such a way as to suppress the interference frequencies. The response signal from the transponder with the superimposed background noise is received by the interrogation device and routed through the adaptive filter which acts to suppress the interference frequencies. The signal available at the output of the filter can then be demodulated for the purpose of reading the data stored.

Abstract: The method includes forming a pad oxide, a polysilicon layer over a substrate. Next, an oxide layer is formed over the polysilicon layer. An opening is formed in the oxide layer, the polysilicon layer, and the pad layer. A trench is formed by etching the substrate using the oxide layer as a mask. A sidewall structure is then formed on the opening. Next, an exposed portion of the substrate is etched by using the sidewall structure as a mask. The sidewall structure and the oxide layer are then removed. An oxide and an oxynitride layer are then formed on the aforesaid feature. A semiconductor layer is then formed over the oxynitride layer. A portion of the semiconductor layer is oxidized for forming an insulating layer. Finally, a refilling layer is formed over the insulating layer and the substrate is planarized for having a planar surface.

Abstract: An improved mold system (20) is provided. The mold system (20) includes a mold (30) having a mold cavity (28). A pot (22) is connected to the mold cavity (28) through a boomerang runner system (24). The boomerang runner system may include a boomerang passage (25) having an inner curvilinear surface (44) and an outer curvilinear surface (42).

Abstract: A semiconductor device (2) includes gates (20, 22, 24, 26), source/drain regions (40, 42, 44, 46), and self-aligned contacts (80, 82, 84, 86). Each self-aligned contact (80, 82, 84, 86) includes a polysilicon layer (50) overlying the associated source/drain region (40, 42, 44, 46). The polysilicon layer (50) may include different doped regions (52, 58) in accordance with the design and function of the device (2).

Abstract: A preferred embodiment of this invention includes an oxidizable layer (e.g. tantalum 48), an oxygen gettering layer (e.g. platinum/tantalum mixture 34) overlaying the oxidizable layer, a noble metal layer (e.g. platinum 36) overlaying the oxygen gettering layer, and a high-dielectric-constant material layer (e.g. barium strontium titanate 38) overlaying the noble metal layer. The novel structures presented provide electrical connection to high-dielectric-constant materials without the disadvantages of current structures. The oxygen gettering layer controls oxygen diffusion, minimizing the formation of a resistive layer either in the lower electrode or at the lower electrode/substrate interface. The oxygen gettering layer acts as a gettering site for oxygen, where the oxygen oxidizes the reactive metal portion of the layer, leaving the noble metal portion of the layer intact. While the oxides/suboxides (e.g.