Abstract: The nanometer-gate MOSFET device of the present invention comprises a shallow-trench-isolation structure; a pair of second conductive sidewall spacers being formed over each inner sidewall of a gate region and on a portion of a first conductive layer and a first raised field-oxide layers for forming an implant region in a central portion of a channel; a buffer-oxide layer being formed over each sidewall of the gate region for forming lightly-doped source/drain diffusion regions; a first sidewall dielectric spacer being formed over each sidewall of the buffer-oxide layers for forming heavily-doped source/drain diffusion regions; a second sidewall dielectric spacer being formed over each sidewall of the first sidewall dielectric spacers for forming a metal-silicide layer over each of heavily-doped source/drain diffusion regions; and a highly conductive-gate structure being formed in the gate region.

Abstract: The scalable stack-type DRAM memory structure of the present invention comprises a scalable DRAM transistor structure and a scalable DRAM capacitor structure. The scalable DRAM transistor structure comprises a plurality of transistor-stacks, a plurality of common-drain regions, and a plurality of source regions being formed over a shallow-trench-isolation structure without a dummy-transistor structure by using a spacer-formation technique. The scalable DRAM capacitor structure comprises a plurality of rectangular tube-shaped cavities being formed over thin fourth conductive islands to form a high-capacity DRAM capacitor for each of DRAM cells; and a plurality of planarized conductive contact-islands over planarized third conductive islands being patterned and simultaneously etched with a plurality of bit-lines for forming a contactless DRAM memory. The cell size of a DRAM cell is scalable and can be made to be smaller than 6F2.

Abstract: A method and system utilizing both (x, y) coordinate (“spatial”) stroke data and associated pressure information for improved handwriting recognition. The method and system can also be applied to all types of handwriting-based data entry applications and also to user authentication. The digitizer pad used in the computer system gives both spatial information and associated pressure data when a stroke is being drawn thereon, e.g., by a stylus. Pressure information can be used to differentiate between different character sets, e.g., upper case and lower case characters for certain alphabetic characters. The spatial stroke data then identifies the particular character. The pressure information can also be used to adjust any display attribute, such as character font size, font selection, color, italic, bold, underline, shadow, language, etc. The associated pressure information can also be used for recognizing a signature. In this case, a user is allowed to sign a name on the digitizer pad.

Abstract: An improved chair having a simplified height-adjustable back arrangement. The back arrangement is defined principally by a back shell provided with support sleeves adjacent opposite sides thereof. The support sleeves are slidably supported on respective uprights which project upwardly adjacent opposite sides of the chair seat. A manually-releasable latching mechanism cooperates between each support sleeve and its respective upright whereby a seated occupant, by using right and left hands, can simultaneously release both latching mechanisms and effect vertical slidable displacement of the back shell to adjust the position thereof.

Abstract: A vertical DRAM cell structure is disclosed by the present invention, in which a trench structure comprises a deep-trench region having a vertical transistor and a second-type STI region being formed in a side portion of the deep-trench region and a common-drain structure comprises different implant regions under a common-drain diffusion region being formed in another side portion of the deep-trench region. The vertical DRAM cell structure is used to implement two contactless DRAM arrays. A first-type contactless DRAM array comprises a plurality of metal bit-lines integrated with planarized common-drain conductive islands and a plurality of highly conductive word-lines. A second-type contactless DRAM array comprises a plurality of metal word-lines integrated with planarized common-gate conductive islands and a plurality of common- drain conductive bit-lines.

Abstract: A self-aligned lateral-transistor DRAM cell structure is disclosed by the present invention, in which a trench structure comprises a trench region and a trench-isolation region being formed in a side portion of the trench region and a self-aligned lateral-transistor structure comprises a merged common-source diffusion region, a self-aligned gate-stack region, and a self-aligned common-drain diffusion region being formed in another side portion of the trench region by using spacer-formation techniques. The unit cell size of the self-aligned lateral-transistor DRAM cell structure can be fabricated to be equal to 6F2 or smaller. The self-aligned lateral-transistor DRAM cell structure is used to implement two contactless DRAM arrays for high-speed read and write operations.

Abstract: In general, in one aspect, the disclosure describes a method of processing content for distribution over a computer network. The method includes receiving submitted electronic content, accessing identification of at least one of a set of more than one electronic book digital rights management (DRM) systems, and automatically generating an electronic book from the received electronic content for distribution in accordance with the identified electronic book digital rights management system(s).

Abstract: The invention provides various configurations, apparatus, methods and systems for anti-theft protection of information storage media generally comprising locking the media between opposing pieces that must be decoupled before the media may be used. In one embodiment, media packaging is equipped with a locking device. The locking device includes a head that is connected to a base by a stem. The head includes an engagement surface beneath which a locking hub mechanism is locked. The mechanism includes spring loaded locking members that are biased towards a locking hub center. The locking device is unlocked by a release device which forces the locking members away from the locking hub center, thereby disengaging the locking hub from the post.

Abstract: A system and method for installing an application on a client device (e.g., a palmtop computer system) communicatively coupled to a host device (e.g., a host computer system). Instead of transferring an application to the client device from another client device, the client device receives a description of the application from the other client device. When the client device and the host device are synchronized, the description is automatically communicated by the client device to the host device, which is also in communication with a source (e.g., an application source). Additional information, such as the type of hardware or the type of operating system used by the client device, is also automatically communicated to the host device by the client device. The host device communicates to the source a specification comprising the description of the application as well as the additional information pertaining to the client device. The host device receives from the source a software element (e.g.

Abstract: A self-aligned vertical transistor DRAM structure comprising a self-aligned trench structure and a self-aligned common-drain structure are disclosed by the present invention, in which the self-aligned trench structure comprises a deep-trench capacitor region having a vertical transistor and a second-type shallow-trench-isolation region being defined by a spacer technique and the self-aligned common-drain structure comprises a common-drain region being defined by another spacer technique. The self-aligned vertical transistor DRAM structure is used to implement two contactless DRAM arrays. A first-type contactless DRAM array comprises a plurality of metal bit-lines integrated with planarized common-drain conductive islands and a plurality of highly conductive word-lines. A second-type contactless DRAM array comprises a plurality of metal word-lines integrated with planarized common-gate conductive islands and a plurality of common-drain conductive bit-lines.

Abstract: A vertical transistor DRAM structure is disclosed by the present invention, in which a trench structure comprises a deep-trench region having a vertical transistor and a second-type shallow-trench-isolation region being formed in a side portion of the deep-trench region and a common-drain structure comprises different implant regions being formed under a common-drain diffusion region in another side portion of the deep-trench region. The vertical transistor DRAM structure is used to implement two contactless DRAM arrays. A first-type contactless DRAM array comprises a plurality of metal bit-lines integrated with planarized common-drain conductive islands and a plurality of highly conductive word-lines. A second-type contactless DRAM array comprises a plurality of metal word-lines integrated with planarized common-gate conductive islands and a plurality of common- drain conductive bit-lines.

Abstract: A self-aligned vertical transistor DRAM structure comprising a self-aligned trench structure and a self-aligned common-drain structure are disclosed by the present invention, in which the self-aligned trench structure comprises a deep-trench capacitor region having a vertical transistor and a second-type shallow-trench-isolation region being defined by a spacer technique and the self-aligned common-drain structure comprises a common-drain region being defined by another spacer technique. The self-aligned vertical transistor DRAM structure is used to implement two contactless DRAM arrays. A first-type contactless DRAM array comprises a plurality of metal bit-lines integrated with planarized common-drain conductive islands and a plurality of highly conductive word-lines. A second-type contactless DRAM array comprises a plurality of metal word-lines integrated with planarized common-gate conductive islands and a plurality of common-drain conductive bit-lines.

Abstract: A connector includes a tubular wall on a first body containing a lamp envelope, coaxially receiving an insulating tube mounted on a second body having a cavity that receives the first body, spring metal strip terminals on the outside of the tubular wall in resilient contact with spring metal strip terminals on the inside of the cavity, and microprocessor controlled heated and cooled air delivered to the lamp envelope by way of the insulating tube in response to a sensor that monitors at least one of lamp amalgam temperature and lamp radiation.

Abstract: Methods are provided for evaluating a biological condition of a subject using a calibrated profile data set derived from a data set having a plurality of members, each member being a quantitative measure of the amount of a subject's RNA or protein as distinct constituents in a panel of constituents. The biological condition may be a naturally occurring physiological state or may be responsive to treatment of the subject with one or more agents. Calibrated profile data sets may be used as a descriptive record for an agent.

Abstract: A self-aligned trench-type DRAM structure comprising a self-aligned DRAM capacitor structure and a self-aligned DRAM transistor structure are disclosed by the present invention, in which the self-aligned DRAM capacitor structure comprises a deep-trench capacitor region and a shallow-trench-isolation region being defined by a spacer technique and the self-aligned DRAM transistor structure comprises a scalable gate-stack region and a common-drain region being defined by another spacer technique. The self-aligned trench-type DRAM structure is used to implement two contactless DRAM arrays. A first-type contactless DRAM array comprises a plurality of metal bit-lines integrated with planarized common-drain conductive islands and a plurality of highly conductive word-lines. A second-type contactless DRAM array comprises a plurality of metal word-lines integrated with planarized conductive-gate islands and a plurality of common-drain conductive bit-lines.

Abstract: A system and method for changing data displayed on a touch-sensitive display screen. The present system and method recognize handwritten strokes made with a stylus on the touch-sensitive display screen of a PDA or palmtop computer in order to alter or correct displayed data. In one mode of operation, computer controlled association of the location of the handwritten strokes on the display screen with one or more of the displayed characters will result in automatic replacement of those characters by the handwritten strokes. In a second mode of operation, matching at least one of the handwritten strokes with one character of the displayed data will result in replacement of one or more characters of the displayed data with the handwritten characters. With the present system and method, the number of steps required to alter displayed data is reduced to the number of handwritten strokes. A significant reduction in time and effort as well as a simplification in application is therefore offered.

Abstract: The scalable stack-type DRAM memory structure of the present invention comprises a scalable DRAM transistor structure and a scalable DRAM capacitor structure. The scalable DRAM transistor structure comprises a plurality of transistor-stacks, a plurality of common-drain regions, and a plurality of source regions being formed over a shallow-trench-isolation structure without a dummy-transistor structure by using a spacer-formation technique. The scalable DRAM capacitor structure comprises a plurality of rectangular tube-shaped cavities being formed over thin fourth conductive islands to form a high-capacity DRAM capacitor for each of DRAM cells; and a plurality of planarized conductive contact-islands over planarized third conductive islands being patterned and simultaneously etched with a plurality of bit-lines for forming a contactless DRAM memory. The cell size of a DRAM cell is scalable and can be made to be smaller than 6F2.

Abstract: The process management system includes task information indicative of tasks that define process steps for a group of processes. The task information defines the steps as software events and as non-software events. The system further includes task relationship information indicative of a relationship between the tasks to define the processes, and application information defining the software events. A user interface displays the tasks and enables the selection of the tasks. The processes are completed by selecting the tasks associated with a particular process and executing the software events and the non-software events corresponding to the selected tasks.