Abstract: According to one embodiment, a memory system includes a non-volatile memory, a memory interface that reads data recorded in the non-volatile memory as a received value, a converting unit that converts the received value to first likelihood information by using a first conversion table, a decoder that decodes the first likelihood information, a control unit that outputs an estimated value with respect to the received value, which is a decoding result obtained by the decoding, when decoding by the decoder has succeeded, and a generating unit that generates a second conversion table based on a decoding result obtained by the decoding, when decoding of the first likelihood information by the decoder has failed. When the generating unit generates the second conversion table, the converting unit converts the received value to the second likelihood information by using the second conversion table, and the decoder decodes the second likelihood information.

Abstract: According to one embodiment, three bits stored in one memory cell of a nonvolatile memory correspond to three pages. In first page writing, a threshold voltage becomes within a first or second region base on a bit value. In second page writing, if being within the first region, it becomes within the first or fourth region; and if being within the second region, it becomes within the second or third region. In the third page writing, if being within the first region, it becomes within the first or sixth region; if being within the second region, it becomes within the second or seventh region; being within the third region, it becomes within the third or eighth region; and if being within the fourth region, it becomes within the fourth or fifth region.

Abstract: According to one embodiment, a memory system receives from a host a first write request including a first block identifier designating a first write destination block to which first write data is to be written. The memory system acquires the first write data from a write buffer temporarily holding write data corresponding to each of the write requests, and writes the first write data to a write destination page in the first write destination block. The memory system releases a region in the write buffer, storing data which is made readable from the first write destination block by writ the first write data to the write destination page. The data made readable is a data of a page in the first write destination block preceding the write destination page.

Abstract: A semiconductor device capable of communicating with a host apparatus includes a symbol generation unit, a coding unit, and a transmission unit. The symbol generation unit includes a random number generation circuit and generates a symbol according to a random number generated by the random number generation circuit. The coding unit performs 8b/10b coding for the symbol. The transmission unit transmits the symbol coded by the 8b/10b coding unit to the host apparatus.

Abstract: A method of managing data storage using a management device that includes determining respective status information for a plurality of storage devices, and calculating, based on the status information, a respective cost for each of the plurality of storage devices using a cost function that includes one or more parameters including at least one of: a program/erase (P/E) parameter, a block error state parameter, a block error level parameter, and a workload parameter. The method further includes selecting a destination storage device of the plurality of storage devices based on at least some of the calculated costs, and writing data to the destination storage device.

Abstract: A polishing apparatus includes a holder holding a target. A polisher polishes the target. An irradiator irradiates the target with an irradiation light from below the polisher. A photoreceiver receives a reflection light reflected from the polishing target to detect a relation between a wavelength and a light quantity of the reflection light. A first reflector bends the irradiation light from the irradiator in a direction tilted to the polishing target. A second reflector bends the reflection light from the polishing target to the photoreceiver. The first reflector irradiates the polishing target with the irradiation light in a direction tilted to the polishing target.

Abstract: A semiconductor device includes: a first semiconductor substrate and a logic circuit provided on the first semiconductor substrate; a memory cell provided above the logic circuit and a second semiconductor substrate provided above the memory cell; a bonding pad provided above the second semiconductor substrate and electrically connected to the logic circuit; and a wiring provided above the second semiconductor substrate. The wiring is electrically connected to the memory cell, and includes at least one of a data signal line, a control voltage line, and a power supply line.

Abstract: A device includes: a substrate; a first wiring layer above the substrate; a second wiring layer above the first wiring layer; a first insulating film on the first and second wiring layers; a second insulating film in the first insulating film, provided at a position overlapping with a part of the first wiring layer and a part of the second wiring layer in a first direction perpendicular to a surface of the substrate, and including a first portion higher than an upper surface of an end portion of the second wiring layer and a second portion lower than the upper surface of the end portion of the second wiring layer; and a plug via the second insulating film in the first insulating film, provided on the upper surface of the end portion of the second wiring layer, and electrically connected to the second wiring layer.

Abstract: According to one embodiment, an image data of a measurement object including a pattern is acquired. First data is acquired by extracting a contour of an element in composition of the pattern from the image data. Second data that specifies a design data of the measurement object and the pattern of the measurement object is acquired. The design data includes a pattern data. A measurement pattern is extracted by using the first data and the second data. An evaluation value for the measurement pattern with respect to the design data is calculated based on the difference between the measurement pattern and the design data.

Abstract: A method of controlling a memory device includes receiving an address indicating a region in a memory cell array and generating one or more voltages supplied to the memory cell array in parallel with receiving the address.

Abstract: According to one embodiment, a polymer material is disclosed. The polymer material contains a polymer. The polymer contains a first monomer unit having a lone pair and an aromatic ring at a side chain, and a second monomer unit including a crosslinking group at a terminal of the side chain, with its molar ratio of 0.5 mol % to 10 mol % to all monomer units in the polymer. The polymer material can be used for manufacturing a composite film as a mask pattern for processing a target film on a substrate. The composite film can be formed by a process including, forming an organic film on the target film with the polymer material, patterning the organic film, and forming the composite film by impregnating a metal compound into the patterned organic film.

Abstract: According to one embodiment, a semiconductor memory includes: a first bit line; a first select transistor having a first terminal connected to the first bit line; a first memory cell connected to a second terminal of the first select transistor; a circuit connected to the first bit line and applying an erase voltage to be applied to the first memory cell to the bit line via the first terminal and the second terminal; and a diode connected to the first bit line and the first circuit.

Abstract: A semiconductor memory device includes a substrate, gate electrodes arranged in a thickness direction of the substrate, first and second semiconductor layers, a gate insulating film, and a first contact. The first semiconductor layer extends in the thickness direction and faces the gate electrodes. The gate insulating film is between the gate electrodes and the first semiconductor layer. The second semiconductor layer is between the substrate and the gate electrodes and connected to a side surface of the first semiconductor layer in a surface direction. The first contact extends in the thickness direction and electrically connected to the second semiconductor layer. The second semiconductor layer includes a first region in contact with the side surface of the first semiconductor layer and containing P-type impurities, and a first contact region electrically connected to the first contact and having a higher concentration of N-type impurities than the first region.

Abstract: According to one embodiment, a memory system includes a nonvolatile memory and a memory controller. The memory controller is configured: to store, in a buffer, a data set read from a cell unit, and an expected data set generated by an error correction on the data set; to count a number of first and second memory cells corresponding to a first and a second combination of data in the data set and the expected data set, respectively, among the memory cells in the cell unit; to calculate a shift amount of a read voltage used in a read operation from the cell unit, based on the number of the first and second memory cells; and to apply the shift amount to a next read operation from the first cell unit.

Abstract: A semiconductor device includes a semiconductor chip with bonding pads, the bonding pads being arranged along one side of an element forming surface of the semiconductor chip, a lead frame including first and second internal leads arranged such that tips thereof correspond to some of the bonding pads of the semiconductor chip, and first and second bonding wires by which the first internal leads and the some of the bonding pads are bonded to each other. The semiconductor device further includes a hanging pin section provided on the element non-forming surface of the semiconductor chip, and a sealing member with which the semiconductor chip is sealed including the hanging pin section and a bonding section between the first and second internal leads and the first and second bonding wires.

Abstract: In a manufacturing method of a semiconductor device according to one embodiment, a first gas containing a first metal element is introduced into a chamber having a substrate housed therein. Next, the first gas is discharged from the chamber using a purge gas. Subsequently, a second gas reducing the first gas is introduced into the chamber. Next, the second gas is discharged from the chamber using the purge gas. Further, a third gas different from the first gas, the second gas, and the purge gas is introduced into the chamber at least either at a time of discharging the first gas or at a time of discharging the second gas.

Abstract: According to one embodiment, a storage device includes a non-volatile memory, an interface circuit, a first control circuit, a wireless transmitting and receiving circuit, and a second control circuit. The interface circuit is electrically connected to the host device and is capable of communicating the host device. The first control circuit performs control of writing write data received from the host device via the interface circuit into the non-volatile memory. The wireless transmitting and receiving circuit is capable of wirelessly communicating with a wireless device. The second control circuit determines whether or not the write data include a predetermined type of data based on measurement data of the write data, and stops wireless communication performed by the wireless transmitting and receiving circuit if it is determined that the write data include the predetermined type of data.

Abstract: According to one embodiment, a memory system includes a semiconductor memory and a controller. The semiconductor memory includes first blocks including a memory cell capable of storing data of one bit, a second block including a memory cell capable of storing data of two or more bits. The semiconductor memory stores first data in a first latch circuit, and second data in a second latch circuit, and writes the first data into one of the first blocks in page units, and the second data into one of the first blocks in page units. The semiconductor memory writes data of at least two pages into the second block, using the first data stored in the first latch circuit and the second data stored in the second latch circuit.

Abstract: According to one embodiment, a nonvolatile semiconductor memory device is connectable to a controller. The nonvolatile semiconductor memory device includes a cell array and a control circuit. The cell array includes a plurality of blocks. The control circuit executes program operations for a plurality of pages included in a write destination block of the blocks, in a certain program order. The write destination block is selected by the controller from the blocks. The control circuit is configured to notify a page address corresponding to a next program operation with respect to the write destination block to the controller.

Abstract: According to one embodiment, a semiconductor memory device includes: a first memory cell; a second memory cell; a first word line; a second word line; and a first bit line. The first memory cell faces the second memory cell. When reading data from the first memory cell, the semiconductor memory device is configured to perform the first operation in which a first voltage is applied to the first word line and a second voltage higher than the first voltage is applied to the second word line, and perform the second operation in which a third voltage higher than the first voltage and a fourth voltage different from the third voltage are applied to the first word line and a fifth voltage lower than the second to the fourth voltage is applied to the second word line.