Abstract: A semiconductor memory device according to an embodiment includes a substrate, first and second conductive layers, first and second pillars, and a first member. The first conductive layer includes a first portion, a second portion, and a third portion above the second portion. The second conductive layers are stacked above the first conductive layer. The first pillar includes a first semiconductor layer in contact with the first portion in a direction crossing the stacked direction. The second pillar is provided to penetrate the second conductive layers and the third portion in the stacked direction. The first member is provided between the first and second pillars and between the second and third portions.

Abstract: A storage device includes a controller configured to control the storage device, and a storage area for security information, the security information including flag information indicating whether reading or writing of data from/to the storage device is permitted and time information indicating a cumulative time value during which power of the storage device has been turned on. When a first command is received from a host device, the controller generates encrypted data by encrypting data obtained by combining the time information and the security information, and after transmitting the encrypted data to the host device, shifts the storage device to a low power state.

Abstract: A semiconductor memory device includes a first and second substrates; and a first and second element layers respectively provided on an upper surface of the first and the second substrates. The first and second substrates respectively include a first and second vias. The first and second element layers respectively includes a first and second pads respectively electrically coupled to the first and second vias, and respectively provided on an upper surface of the first and second element layers. The upper surface of the second element layer is arranged so as to be opposed to the upper surface of the first element layer. The first and second pads are electrically coupled and symmetrically arranged with respect to a surface where the first and second element layers are opposed to each other.

Abstract: A memory system according to an embodiment includes a semiconductor memory, and a memory controller. The semiconductor memory comprises memory cells and word lines. Each of the word lines is connected to the memory cells. The memory controller executes a patrol operation including a read operation of the semiconductor memory. The word lines are classified into one of first and second groups. The memory controller executes patrol operations in which the word lines are respectively selected in a first patrol period and, in a second patrol period subsequent to the first patrol period, executes a patrol operation in which the word line included in the first group is selected and omits a patrol operation in which the word line included in the second group is selected.

Abstract: A memory system includes a nonvolatile memory, a memory controller included in a first package, and a memory interface circuit included in a second package that is different from the first package. The memory controller includes an encoder for performing encoding for error correction. The memory controller is configured to encode first data into second data using the encoder, and program the second data into a location in the nonvolatile memory. The memory interface circuit is interposed between the memory and the memory controller. The memory interface circuit includes a decoder for performing decoding for error correction. The memory interface circuit is configured to read third data from a first location in the nonvolatile memory, diagnose the third data by decoding the third data using the decoder, and convey a result of the diagnosis to the memory controller.

Abstract: According to one embodiment, a magnetic device includes: a first magnetic material provided above a substrate; a second magnetic material provided between the substrate and the first magnetic material; a nonmagnetic material provided between the first magnetic material and the second magnetic material; a first layer provided between the substrate and the second magnetic material and including an amorphous layer; and a second layer provided between the amorphous layer and the second magnetic material and including a crystal layer.

Abstract: According to one embodiment, a method for manufacturing a magnetoresistive memory device includes forming a first layer stack on a substrate. A second layer stack including a first ferromagnet is formed on the first layer stack. A mask including a first portion and an opening is formed above the second layer stack. The second layer stack is etched with an ion beam that travels through the opening. The first layer stack is etched by reactive ion etching through the opening.

Abstract: A magnetic memory according to an embodiment includes: a magnetic member having a cylindrical form, the magnetic member including a first end portion and a second end portion and extending in a first direction from the first end portion to the second end portion, the first end portion having an end face, which includes a face inclined with respect to a plane perpendicular to the first direction.

Abstract: According to one embodiment, a memory system includes a non-volatile semiconductor memory, a block management unit, and a transcription unit. The semiconductor memory includes a plurality of blocks to which data can be written in both the first mode and the second mode. The block management unit manages a block that stores therein no valid data as a free block. When the number of free blocks managed by the block management unit is smaller than or equal to a predetermined threshold value, the transcription unit selects one or more used blocks that stores therein valid data as transcription source blocks and transcribes valid data stored in the transcription source blocks to free blocks in the second mode.

Abstract: A memory system includes a nonvolatile memory, an interface circuit, and a controller configured to upon receipt of a plurality of write commands for storing write data in the nonvolatile memory via the interface circuit, acquire compression-ratio information about the write data associated with each write command, determine a compression ratio of each write data based on the acquired compression-ratio information, and determine an execution order of the write commands based on the determined compression ratio.

Abstract: According to one embodiment, a memory system includes a non-volatile memory, a memory interface that reads data recorded in the non-volatile memory as a received value, a converting unit that converts the received value to first likelihood information by using a first conversion table, a decoder that decodes the first likelihood information, a control unit that outputs an estimated value with respect to the received value, which is a decoding result obtained by the decoding, when decoding by the decoder has succeeded, and a generating unit that generates a second conversion table based on a decoding result obtained by the decoding, when decoding of the first likelihood information by the decoder has failed. When the generating unit generates the second conversion table, the converting unit converts the received value to the second likelihood information by using the second conversion table, and the decoder decodes the second likelihood information.

Abstract: According to one embodiment, a substrate processing apparatus includes a table configured to place a substrate thereon and to connect the substrate to a positive electrode, an counter electrode located opposite to the table, having a plurality of holes, and connected to a negative electrode, and a holding unit located opposite to the table across the counter electrode and configured to supply a chemical liquid to the counter electrode while holding the counter electrode.

Abstract: According to one embodiment, a semiconductor memory device includes: first and second memory cells; a first and second word lines; and a first bit line. The device is configured to execute first to sixth operations. In the first operation, a first voltage is applied to the first word line and a second voltage is applied to a semiconductor layer. In the second operation, the first voltage is applied to the second word line. In the third operation, a third voltage is applied to the first word line. In the fourth operation, the third voltage is applied to the second word line. In the fifth operation, a fourth voltage is applied to the first word line. In the sixth operation, the fourth voltage is applied to the second word line.

Abstract: According to one embodiment, a superconducting element used as a pixel for detecting a particle is disclosed. The superconducting element includes at least one superconducting strip. The at least one superconducting strip includes a superconducting portion extending in a first direction, including first and second ends and made of a first superconducting material, a first conductive portion connected to the first end of the superconducting portion, and a second conductive portion connected to the second end of the superconducting portion. A superconducting region of the superconducting portion is configured to be dived when the particle is made incident on the superconducting portion along the first direction via the first conductive portion.

Abstract: According to one embodiment, in a first differential amplifier circuit of a semiconductor device, a first transistor receives an input signal at the gate. A second transistor forms a differential pair with the first transistor. The second transistor receives a reference signal at the gate. A third transistor is connected in series with the first transistor. A fourth transistor is connected in series with the second transistor. A fifth transistor is disposed on the output side. The fifth transistor forms a first current mirror circuit with the fourth transistor. A sixth transistor is connected to the drain of the second transistor in parallel with the fourth transistor. The sixth transistor forms a second current mirror circuit with the fifth transistor. A first discharge circuit is connected to the source of the sixth transistor.

Abstract: An optical characteristics measuring device includes a first light source capable of irradiating a sample with light and a second light source capable of irradiating the sample with microwaves. A measuring device measures microwave power of the reflection of the microwaves from the sample. A calculation unit calculates a parameter relating to the electrical conductivity of the sample using the microwave power of the reflected waves measured by the measuring device. A control unit controls the intensity of the light of the first light source so that the parameter becomes approximately a predetermined value. The calculation unit specifies first to n-th intensities of the light at which the parameter becomes approximately the predetermined value for each of the first to n-th wavelengths of the light and obtains relationships between the first to n-th wavelengths and the first to n-th intensities corresponding to the respective first to n-th wavelengths.

Abstract: A storage device includes a first memory, a controller circuit configured to control an access to the first memory, a connector connectable to host apparatuses, and a connection detection circuit configured to detect disconnection of the connector from a host apparatus based on a state of a signal line of the connector.

Abstract: In one embodiment, a semiconductor manufacturing apparatus includes a substrate holder configured to hold a plurality of substrates such that the substrates are arranged in parallel to each other. The apparatus further includes a fluid injector including a plurality of openings that inject fluid to areas in which distances from surfaces of the substrates are within distances between centers of the substrates adjacent to each other, the fluid injector being configured to change injection directions of the fluid injected from the openings in planes that are parallel to the surfaces of the substrates by self-oscillation.

Abstract: A semiconductor storage device includes a first conductive layer, a second conductive layer, a third conductive layer, a contact plug, a memory trench extending between the second conductive layer and the third conductive layer. The memory trench is formed around the contact plug, and surrounds a first area in which the contact plug is disposed. A second area is separated from the first area and includes a pillar penetrating the first conductive layer. The second conductive layer extends between the first and second areas, and is connected to the first conductive layer. The third conductive layer is on the opposite side of the first area to the second area, and is connected to the first conductive layer.

Abstract: According to one embodiment, a communication device includes a control circuit. The control circuit determines an output waveform of the data to be received from an external device. The control circuit stores information relating to the output waveform into a nonvolatile memory in response to determining of the output waveform of the data from among N (N is a natural number of three or more) types of output waveforms. The control circuit determines an output waveform of the data from among M or less types of output waveforms in the N types of output waveforms (M<N) (M is a natural number of N?2 or more) based on the information stored in the nonvolatile memory, when the information is stored in the nonvolatile memory.