Abstract: According to one embodiment, in a semiconductor storage device, a conductive cover is provided on a side of the principal surface, and covers at least a part of the memory and the controller. A substrate has a first notched portion and a second notched portion in an outer edge. The conductive cover has a top plate portion, a first side plate portion, a second side plate portion, a first claw portion, and a second claw portion. The first claw portion is extended from a lower end of the first side plate in a direction intersecting with the principal surface. The first claw portion is fitted into the first notched portion. The second claw portion is extended from a lower end of the second side plate in the direction intersecting with the principal surface. The second claw portion is fitted into the second notched portion.

Abstract: A semiconductor device includes a plurality of high-voltage insulated-gate field-effect transistors arranged in a matrix form on the main surface of a semiconductor substrate and each having a gate electrode, a gate electrode contact formed on the gate electrode, and a wiring layer which is formed on the gate electrode contacts adjacent in a gate-width direction to electrically connect the gate electrodes arranged in the gate-width direction. And the device includes shielding gates provided on portions of an element isolation region which lie between the transistors adjacent in the gate-width direction and gate-length direction and used to apply reference potential or potential of a polarity different from that of potential applied to the gate of the transistor to turn on the current path of the transistor to the element isolation region.

Abstract: A semiconductor memory device includes a first wiring extending in a first direction, a second wiring above the first wiring and extending in a second direction, first and second memory cells electrically connected in parallel between the first and second wirings and each including a phase change material, a first insulating film on a side portion of the first cell facing the second cell in the second direction, a third wiring above the second wiring and extending in the second direction, a fourth wiring above the third wiring and extending in the first direction, third and fourth memory cells electrically connected between the third and fourth wirings in parallel and each including a phase change material, and a second insulating film on a side of the third cell facing the fourth cell in the second direction. The first film has a higher thermal insulation capacity than the second film.

Abstract: According to one embodiment, a semiconductor memory device includes a plurality of memory cells; a first circuit configured to convert first data into second data relating to an order of thresholds of the memory cells; and a second circuit configured to perform a write operation on the memory cells based on the second data.

Abstract: An integrated circuit device of an embodiment includes a substrate, a first transistor, an insulation layer, a first contact, a second contact, and a first single crystal portion. The first transistor includes a first gate electrode, and a first drain region, and wherein the first source region and the first drain region are disposed in the substrate. The first contact faces the first gate electrode. The second contact faces a first region that is first one of the first source region and the first drain region. The first single crystal portion is disposed on the first region and convex from a surface of the first region, and is located between the first region and the second contact.

Abstract: A semiconductor device includes a first rare earth oxide layer, a first magnetic layer adjacent to the first rare earth oxide layer, a second rare earth oxide layer, a second magnetic layer adjacent to the second rare earth oxide layer, and a nonmagnetic layer. The first magnetic layer is disposed between the first rare earth oxide layer and the nonmagnetic layer and is oriented in a crystal surface which is the same as a crystal surface of the nonmagnetic layer. The second magnetic layer is disposed between the second rare earth oxide layer and the nonmagnetic layer and is oriented in a crystal surface which is the same as a crystal surface of the nonmagnetic layer. The nonmagnetic layer is disposed between the first magnetic layer and the second magnetic layer.

Abstract: According to one embodiment, a semiconductor memory device includes a first conductive layer, a first semiconductor body, a second semiconductor body, a first memory layer, and a second memory layer. The first conductive layer includes first to fourth extension regions, and a first connection region. The first extension region extends in a first direction. The second extension region extends in the first direction and is arranged with the first extension region in the first direction. The third extension region extends in the first direction and is arranged with the first extension region in a second direction crossing the first direction. The fourth extension region extends in the first direction, is arranged with the third extension region in the first direction, and is arranged with the second extension region in the second direction.

Abstract: According to one embodiment, a memory system includes a nonvolatile memory and a controller. The controller acquires, from a host, write data having the same first size as a data write unit of the nonvolatile memory and obtained by dividing write data associated with one write command having a first identifier indicating a first write destination block in a plurality of write destination blocks into a plurality of write data or combining write data associated with two or more write commands having the first identifier. The controller writes the acquired write data having the first size to the first write destination block by a first write operation.

Abstract: According to the embodiment, a semiconductor memory device includes a first conductive layer, a second conductive layer, a first memory cell, a second memory cell, a third conductive layer, a first contact, a intermediate memory cell, a fourth conductive layer, a third memory cell, a fifth conductive layer, and a second contact. The third conductive layer is separated from the first conductive layer and the second conductive layer in a third direction crossing a first direction and crossing a second direction and extends in the second direction. The fifth conductive layer is separated from the second conductive layer in the third direction and extends in the second direction. A first length of the second conductive layer along the second direction is shorter than a second length of the fifth conductive layer along the second direction.

Abstract: According to one embodiment, a polymer material is disclosed. The polymer material contains a polymer. The polymer contains a first monomer unit having a lone pair and an aromatic ring at a side chain, and a second monomer unit including a crosslinking group at a terminal of the side chain, with its molar ratio of 0.5 mol % to 10 mol % to all monomer units in the polymer. The polymer material can be used for manufacturing a composite film as a mask pattern for processing a target film on a substrate. The composite film can be formed by a process including, forming an organic film on the target film with the polymer material, patterning the organic film, and forming the composite film by impregnating a metal compound into the patterned organic film.

Abstract: In one embodiment, a semiconductor device includes a first film including a plurality of electrode layers and a plurality of insulating layers provided alternately in a first direction, and a first semiconductor layer provided in the first film via a charge storage layer and extending in the first direction. The device further includes a first conductive member provided in the first film and extending in the first direction, and a second semiconductor layer provided on the first film to contact the first semiconductor layer. The second semiconductor layer includes a first surface on a side of the first film, and a second surface on an opposite side of the first surface. The second surface is an uneven face protruding towards the first direction.

Abstract: According to one embodiment, a memory system includes a nonvolatile memory and a memory controller. The memory controller is configured: to store, in a buffer, a data set read from a cell unit, and an expected data set generated by an error correction on the data set; to count a number of first and second memory cells corresponding to a first and a second combination of data in the data set and the expected data set, respectively, among the memory cells in the cell unit; to calculate a shift amount of a read voltage used in a read operation from the cell unit, based on the number of the first and second memory cells; and to apply the shift amount to a next read operation from the first cell unit.

Abstract: A substrate treatment apparatus according to an embodiment of the present invention includes a chamber, a stage, a gas discharger, a plasma generator, and a rotation mechanism. The stage supports a semiconductor substrate in the chamber. The gas discharger discharges a film formation gas toward the semiconductor substrate from a position opposing the stage. The plasma generator is provided on the gas discharger and generates plasma in the chamber during discharge of the film formation gas. The rotation mechanism rotates the stage during generation of the plasma.

Abstract: According to one embodiment, a template for imprint patterning processes comprises a template substrate having a first surface and a pedestal on the first surface of the template substrate, the pedestal having a second surface spaced from the first surface in a first direction perpendicular to the first surface. A pattern is disposed on the second surface. The pedestal has a sidewall between the first surface and the second surface that is at an angle of less than 90° to the second surface.

Abstract: According to one embodiment, a pattern forming material is disclosed. The pattern forming material contains a polymer. The polymer includes a specific first monomer unit. The monomer unit has a structure having ester of a carboxyl group at a terminal of a side chain. In the ester, a carbon atom bonded to an oxygen atom next to a carbonyl group is a primary carbon, a secondary carbon or a tertiary carbon. The pattern forming material is used for manufacturing a composite film as a mask pattern for processing a target film on a substrate. The composite film is formed by a process including, forming an organic film on the target film with the pattern forming material, patterning the organic film, and forming the composite film by infiltering a metal compound into the patterned organic film.

Abstract: According to the embodiments, a nonvolatile memory device is configured to store a normal operating system, and store a bootloader. A host device is capable of initiating the normal operating system by using the bootloader. The host device is configured to determine whether a first condition is established based on information obtained from the nonvolatile memory device; and rewrite, when determined the first condition is established, the bootloader so that an emergency software is initiated when booting the host device. The emergency software is executed on the host device. The host device is capable of issuing only a read command to the nonvolatile memory device under a control of the emergency software.

Abstract: According to one embodiment, a first liquid is supplied on a first face of a substrate. The first liquid has a pH with which a surface zeta potential of the substrate becomes negative and a surface zeta potential of a foreign substance attaching to the first face becomes positive. Then, a solidified layer in which at least part of the first liquid has been solidified is formed by cooling the substrate down to be equal to or lower than a solidification point of the first liquid. Thereafter, the solidified layer is melted.

Abstract: A correction pattern generation device includes a processor configured to receive pattern information for a mask including a defect in a pattern formed on the mask, generate a correction pattern candidate for correcting the defect, calculate a correction difficulty degree for the correction pattern candidate, and select a correction pattern from correction pattern candidates based on the calculated correction difficulty degree for each correction pattern candidate if more than one correction pattern candidate for correcting the defect is generated.

Abstract: In a manufacturing method of a semiconductor device according to one embodiment, a first gas containing a first metal element is introduced into a chamber having a substrate housed therein. Next, the first gas is discharged from the chamber using a purge gas. Subsequently, a second gas reducing the first gas is introduced into the chamber. Next, the second gas is discharged from the chamber using the purge gas. Further, a third gas different from the first gas, the second gas, and the purge gas is introduced into the chamber at least either at a time of discharging the first gas or at a time of discharging the second gas.

Abstract: A system for reading stored data may include one or more Ethernet drives and a controller, both configured to communicatively connect to a host device. The controller may receive a first read command from the host device, determine a first drive among the one or more Ethernet drives using the first read command and a mapping table, translate the first read command into a second read command, and send the second read command to the first drive. Responsive to receiving the second read command, the first drive may send a first remote data transfer instruction to the host device independent of the controller. The first remote data transfer instruction may include stored data read from the first drive to cause the host device to write the stored data read from the first drive to one or more memory buffers in the host device indicated by the second read command.