Abstract: A magnetic memory device including a first memory cell which includes a first stacked structure including a magnetic layer and a second memory cell which is provided on the first memory cell and includes a second stacked structure including a magnetic layer. Each of the first stacked structure and the second stacked structure includes a first magnetic layer having a variable magnetization direction, a second magnetic layer having a fixed magnetization direction, and a nonmagnetic layer provided between the first magnetic layer and the second magnetic layer. A concentration of iron (Fe) contained in the first magnetic layer included in the first stacked structure and a concentration of iron (Fe) contained in the first magnetic layer included in the second stacked structure are different from each other.

Abstract: A memory includes first and second select gate transistors, memory cells, a source line, a bit line, a selected word line which is connected to a selected memory cell as a target of a verify reading, a non-selected word line which is connected to a non-selected memory cell except the selected memory cell, a potential generating circuit for generating a selected read potential which is supplied to the selected word line, and generating a non-selected read potential larger than the selected read potential, which is supplied to the non-selected word line, and a control circuit which classifies a threshold voltage of the selected memory cell to one of three groups by verifying which area among three area which are isolated by two values does a cell current of the selected memory cell belong, when the selected read potential is a first value.

Abstract: A reliability evaluation apparatus according to the present embodiment is provided with a housing and a board insertable into the housing. A plurality of sockets are provided on the board. Semiconductor devices are respectively attachable to socket. The plurality of sockets have electrodes electrically connectable to terminals of the semiconductor devices. A heater is provided inside the housing. A controller is connected to the plurality of sockets and to the heater. The controller controls a voltage to be applied to the terminal of the semiconductor device and controls an output of the heater. A plurality of electromagnets are arranged inside the housing so as to be positioned above or below the plurality of sockets when the board is inserted into the housing.

Abstract: A semiconductor memory device includes a substrate, a controller, a semiconductor memory component, first and second capacitors, and a jumper element. The substrate has a conductor pattern. The conductor pattern includes a first conductor portion and a second conductor portion. The first conductor portion overlaps at least a part of the first capacitor in a thickness direction of the substrate and is electrically connected to the first capacitor. The second conductor portion overlaps at least a part of the second capacitor in the thickness direction of the substrate and is electrically connected to the second capacitor. The first conductor portion and the second conductor portion are separated from each other, and are electrically connected to each other by the jumper element.

Abstract: According to one embodiment, there is provided an evaluation apparatus including a first data bus and a transmission device. The transmission device is electrically connected to the first data bus at an output side thereof and configured to receive data and another signal different from the data. The transmission device is configured to supply the data to the first data bus in a first period during which a valid signal is in an active level, and supply the another signal to the first data bus in a second period during which the valid signal is in a non-active level.

Abstract: A semiconductor storage device includes a stacked body and a columnar body. The stacked body includes a plurality of conductive layers and a plurality of insulating layers that are alternately stacked in a first direction. The columnar body extends through the stacked body in the first direction and includes a core portion, a channel film, a tunnel oxide film, and a charge storage film in this order from a center portion thereof. The channel film has a first region in contact with the core portion and a second region in contact with the tunnel oxide film. The first region is a semiconductor doped with impurities. The second region is a semiconductor. A concentration of the impurities in the second region is lower than that in the first region.

Abstract: According to one embodiment, a fan scrubber includes an inlet pipe to be connected to a post-stage side of a vacuum pump, in a state where a film preparation apparatus is arranged at a pre-stage before the vacuum pump, a process chamber connected to the inlet pipe, and containing a fan connected to a main shaft of a motor, a heater configured to heat the inlet pipe, and a controller configured to control turning on/off of the heater. The controller turns off the heater, when a signal received from the film preparation apparatus has been switched from a film preparation signal to a cleaning signal.

Abstract: A memory system includes a non-volatile memory and a memory controller. During a read operation to read data stored in the non-volatile memory as an N-dimensional error correction code, where N is two or more, the memory controller performs an error correction process on the N-dimensional error correction code iteratively, the error correction process including a first decoding process on a first decoding input to produce a first decoding output and a second decoding process on a second decoding input to produce a second decoding output. During the error correction process, upon determining that errors remaining in the second decoding output after a most recent iteration would not be correctable, the memory controller performs a next iteration using a first decoding input for the next iteration, which is a modified form of the second decoding output of the most recent iteration.

Abstract: According to one embodiment, a semiconductor storage device includes a first memory string including a first memory transistor, a first word line connected to a gate electrode of the first memory transistor, a source line connected to one end of the memory string, and a first connection transistor connected between the first word line and the source line.

Abstract: In one embodiment, a semiconductor device includes a first chip that includes a first interconnect layer, a first insulator provided on the first interconnect layer, a first metal portion provided on the first interconnect layer and provided in the first insulator and including at least one of palladium, platinum and gold, and a second interconnect layer provided on the first metal portion and provided in the first insulator. The device further includes a second chip that includes a second insulator provided on the first insulator, and a third interconnect layer provided in the second insulator and provided on the second interconnect layer.

Abstract: According to one embodiment, there is provided a semiconductor device comprising a first differential amplifier circuit. The first differential amplifier circuit includes a first transistor, a second transistor, a third transistor, a fourth transistor, a fifth transistor, and a sixth transistor. The second transistor's gate and drain are connected to the first transistor. The third transistor is diode-connected through the first transistor or diode-connected without passing through the first transistor. Thea fourth transistor is diode-connected through the second transistor or diode-connected without passing through the second transistor. The fifth transistor forms a first current mirror circuit with the third transistor. The sixth transistor is connected to a drain of the first transistor in parallel with the third transistor and forms a second current mirror circuit with the fifth transistor.

Abstract: A method of an embodiment separates a bonded substrate including first and second substrates. The bonded substrate includes a carbon film on a first surface of the first substrate, a memory cell on the carbon film, a first connection terminal on the memory cell, a transistor on a first surface of the second substrate, and a second connection terminal on the transistor. In opposing direction of the first surfaces of the first and second substrates, a side of the first substrate on which the memory cell is located and a side of the second substrate on which the transistor is located are joined together, and the first and second connection terminals are mutually connected. The method includes removing the carbon film, and separating the bonded substrate into the first substrate with the first surface exposed and the second substrate on which the memory cell and the transistor are located.

Abstract: An electronic apparatus includes a top plate, a bottom plate provided under the top plate, a circuit board provided between the top plate and the bottom plate, an electronic component disposed on the circuit board, and an intermediate plate provided between the top plate and the circuit board. The intermediate plate is configured to provide a clearance between the top plate and intermediate plate, or between the circuit board and the intermediate plate. The intermediate plate is further configured to allow an air flow from a first end portion to a second end portion of the top plate.

Abstract: According to one embodiment, an inspection device includes a stage on which a substrate having a protrusion portion on a surface thereof is mountable. A ring member presses an outer periphery of the substrate on the stage. A liquid supply unit supplies a liquid on the surface of the substrate from the surface thereof to a first height. An imaging unit captures an image of a surface of the liquid and the protrusion portion from above the surface of the substrate. An arithmetic operation unit determines a size of an exposed portion of the protrusion portion which is exposed from the surface of the liquid by using the image obtained from the imaging unit, and determines a height of the protrusion portion on the basis of the size of the exposed portion.

Abstract: According to one embodiment, a memory system includes a nonvolatile memory and a controller. The controller acquires, from a host, write data having the same first size as a data write unit of the nonvolatile memory and obtained by dividing write data associated with one write command having a first identifier indicating a first write destination block in a plurality of write destination blocks into a plurality of write data or combining write data associated with two or more write commands having the first identifier. The controller writes the acquired write data having the first size to the first write destination block by a first write operation.

Abstract: According to one embodiment, a memory device includes a resistance change memory element including a first electrode, a second electrode, and an intermediate layer provided between the first electrode and the second electrode, containing germanium (Ge), tellurium (Te) and at least one element selected from lithium (Li) and sodium (Na), and at least a part of which being capable of exhibiting a crystalline state.

Abstract: A semiconductor memory device includes a first and second substrates; and a first and second element layers respectively provided on an upper surface of the first and the second substrates. The first and second substrates respectively include a first and second vias. The first and second element layers respectively includes a first and second pads respectively electrically coupled to the first and second vias, and respectively provided on an upper surface of the first and second element layers. The upper surface of the second element layer is arranged so as to be opposed to the upper surface of the first element layer. The first and second pads are electrically coupled and symmetrically arranged with respect to a surface where the first and second element layers are opposed to each other.

Abstract: A memory system includes a nonvolatile memory configured to execute one of a plurality of read operations, including a first read operation and a second read operation, and a memory controller configured to issue a read command to the nonvolatile memory to cause the nonvolatile memory to execute one of the plurality of read operations. The memory controller is configured to receive a read request, estimate a reliability level of a result of a read operation to be executed by the nonvolatile memory to read data from a physical address specified in the read request, select one of the first and second read operations to be executed first in a read sequence corresponding to the read request by the nonvolatile memory based on the estimated reliability level, and instruct the nonvolatile memory to execute the selected read operation.

Abstract: A mask manufacturing method includes stacking a first antireflection layer on a first stacked body at a first film thickness so as to create a first transmissive type mask. In the first stacked body, a first semitransmissive layer, a first reflective layer, and a first transmissive substrate are stacked. The mask manufacturing method includes stacking a second antireflection layer on a second stacked body at a second film thickness so as to create a second transmissive type mask. In the second stacked body, a second semitransmissive layer, a second reflective layer, and a second transmissive substrate are stacked. The second film thickness is determined in accordance with a thermal expansion amount of the first mask.

Abstract: A semiconductor storage device according to an embodiment comprises a substrate. A stack body having first conductive layers and first insulating layers alternately stacked in a first direction is provided on the substrate. A pillar part extends in the first direction in the stack body and has a memory film. An insulating member extends in the first direction at a position different from that of the pillar part in the stack body. A phosphorus-containing insulator is provided below the stack body and the insulating member.