Abstract: A circuit includes a selection circuit configured to receive a first address at a first input and a second address at a second input, pass the first address to an output when a select signal has a first logical state, and pass the second address to the output when the select signal has a second logical state different from the first logical state. The circuit also includes a decoder configured to decode the passed first address or second address.
Type:
Grant
Filed:
September 25, 2019
Date of Patent:
March 2, 2021
Assignees:
TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY LTD., TSMC CHINA COMPANY, LIMITED, TSMC NANJING COMPANY, LIMITED
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