Abstract: Structure and methods of making the structures. The structures include a structure, comprising: an organic dielectric passivation layer extending over a substrate; an electrically conductive current spreading pad on a top surface of the organic dielectric passivation layer; an electrically conductive solder bump pad comprising one or more layers on a top surface of the current spreading pad; and an electrically conductive solder bump containing tin, the solder bump on a top surface of the solder bump pad, the current spreading pad comprising one or more layers, at least one of the one or more layers consisting of a material that will not form an intermetallic with tin or at least one of the one or more layers is a material that is a diffusion barrier to tin and adjacent to the solder bump pad.

Abstract: Systems and methods for forming a time-average line image are disclosed. The method includes forming a line image with a first amount of intensity non-uniformity. The method also includes forming and scanning a secondary image over at least a portion of the line image to form a time-averaged modified line image having a second amount of intensity non-uniformity that is less than the first amount. Wafer emissivity is measured in real time to control the intensity of the secondary image. Temperature is also measured in real time based on the wafer emissivity and reflectivity of the secondary image, and can be used to control the intensity of the secondary image.

Abstract: Solder mold plates and methods of manufacturing the solder mold plates are provided herein. The solder mold plates are used in controlled collapse chip connection processes. The solder mold plate includes a plurality of cavities. At least one cavity of the plurality of cavities has a different volume than another of the cavities in a particular chip set site. The method of manufacturing the solder mold plate includes determining susceptible white bump locations on a chip set. The method further includes forming lower volume cavities on the solder mold plate which coincide with the susceptible white bump locations, and forming higher volume cavities on the solder mold plate which coincide with less susceptible white bump locations.

Abstract: Structure and methods of making the structures. The structures include a structure, comprising: an organic dielectric passivation layer extending over a substrate; an electrically conductive current spreading pad on a top surface of the organic dielectric passivation layer; an electrically conductive solder bump pad comprising one or more layers on a top surface of the current spreading pad; and an electrically conductive solder bump containing tin, the solder bump on a top surface of the solder bump pad, the current spreading pad comprising one or more layers, at least one of the one or more layers consisting of a material that will not form an intermetallic with tin or at least one of the one or more layers is a material that is a diffusion barrier to tin and adjacent to the solder bump pad.

Abstract: A phase-shift mask having a checkerboard array and a surrounding sub-resolution assist phase pattern. The checkerboard array comprises alternating phase-shift regions R that have a relative phase difference of 180 degrees. The sub-resolution assist phase regions R? reside adjacent corresponding phase-shift regions R and have a relative phase difference of 180 degrees thereto. The sub-resolution assist phase regions R? are configured to mitigate undesirable edge effects when photolithographically forming photoresist features. Method of forming LEDs using the phase-shift mask are also disclosed.

Abstract: Apparatuses and methods are provided for processing a substrate having an upper surface that includes a central region, a peripheral region, and an edge adjacent to the peripheral region. An image having an intensity sufficient to effect thermal processing of the substrate is scanned across the upper surface of the substrate. The image scanning geometry allows processing the central region of the substrate at a substantially uniform temperature without damaging the outer edge. In some instances, the image may be formed from a beam traveling over at least a portion of the central region so that no portion thereof directly illuminates any portion of the edge when the image is scanned across the periphery region. The substrate may be rotated 180° or the beam direction may be switched after part of the scanning operation has been completed.

Abstract: An interconnection structure suitable for flip-chip attachment of microelectronic device chips to packages, comprising a two, three or four layer ball-limiting metallurgy including an adhesion/reaction barrier layer, and having a solder wettable layer reactive with components of a tin-containing lead free solder, so that the solderable layer can be totally consumed during soldering, but a barrier layer remains after being placed in contact with the lead free solder during soldering. One or more lead-free solder balls is selectively situated on the solder wetting layer, the lead-free solder balls comprising tin as a predominant component and one or more alloying components.

Abstract: Systems and methods for performing ultrafast laser annealing in a manner that reduces pattern density effects in integrated circuit manufacturing are disclosed. The method includes scanning at least one first laser beam over the patterned surface of a substrate. The at least one first laser beam is configured to heat the patterned surface to a non-melt temperature Tnonmelt that is within about 400° C. of the melt temperature Tmelt. The method also includes scanning at least one second laser beam over the patterned surface and relative to the first laser beam. The at least one second laser beam is pulsed and is configured to heat the patterned surface from the non-melt temperature provided by the at least one first laser beam up to the melt temperature.

Abstract: Sub-field enhanced global alignment (SEGA) methods for aligning reconstituted wafers in a lithography process are disclosed. The SEGA methods provide the ability to accommodate chip placement errors for chips supported by a reconstituted wafer when performing a lithographic process having an overlay requirement. The SEGA methods include measuring chip locations to determine sub-fields of the reconstituted wafer over which enhanced global alignment (EGA) can be performed on the chips therein to within the overlay requirement. The SEGA methods further included individually performing EGA over the respective sub-fields. The SEGA methods take advantage of the benefits of both EGA and site-by-site alignment and are particularly applicable to wafer-level packing lithographic processes such as fan-out wafer-level packaging.

Abstract: Apparatuses and methods are provided for processing a surface of a substrate. The substrate may have a surface pattern that exhibits directionally and/or orientationally different reflectivities relative to radiation of a selected wavelength and polarization. The apparatus may include a radiation source that emits a photonic beam of the selected wavelength and polarization directed toward the surface at orientation angle and incidence angle selected to substantially minimize substrate surface reflectivity variations and/or minimize the maximum substrate surface reflectivity during scanning. Also provided are methods and apparatuses for selecting an optimal orientation and/or incidence angle for processing a surface of a substrate.

Abstract: Provided are apparatuses and method for the thermal processing of a substrate surface, e.g., controlled laser thermal annealing (LTA) of substrates. The invention typically involves irradiating the substrate surface with first and second images to process regions of the substrate surface at a substantially uniform peak processing temperature along a scan path. A first image may serve to effect spike annealing of the substrates while another may be used to provide auxiliary heat treatment to the substrates before and/or after the spike annealing. Control over the temperature profile of the prespike and/or postspike may also reduce stresses and strains generated in the wafers. Also provided are microelectronic devices formed using the inventive apparatuses and methods.

Abstract: Methods and apparatuses are provided for improving the intensity profile of a beam image used to process a semiconductor substrate. At least one photonic beam may be generated and manipulated to form an image having an intensity profile with an extended uniform region useful for thermally processing the surface of the substrate. The image may be scanned across the surface to heat at least a portion of the substrate surface to achieve a desired temperature within a predetermined dwell time. Such processing may achieve a high efficiency due to the large proportion of energy contained in the uniform portion of the beam.

Abstract: Provided are systems and methods for processing the surface of substrates that scan a laser beam at one or more selected orientation angles. The orientation angle or angles may be selected to reduce substrate warpage. When the substrates are semiconductor wafers having microelectronic devices, the orientation angles may be selected to produce controlled strain and to improve electronic performance of the devices.

Abstract: A method of aligning a wafer when lithographically fabricating a light-emitting diode (LED). The method includes forming on the wafer at least one roughened alignment mark having a root-mean-square (RMS) surface roughness ?S. The roughened alignment mark is formed as a consequence of forming a plasma etch to roughen a LED surface on which the wafer alignment mark resides. The method also includes imaging the at least one roughened wafer alignment mark with alignment light having a wavelength ?A that is in the range from about 2?S to about 8?S. The method also includes comparing the detected image to an alignment reference to establish wafer alignment. Once wafer alignment is established, p-contacts and n-contacts can be formed on the LED upper surface in their proper locations.

Abstract: Provided are apparatuses and method for the thermal processing of a substrate surface, e.g., controlled laser thermal annealing (LTA) of substrates. The invention typically involves irradiating the substrate surface with first and second images to process regions of the substrate surface at a substantially uniform peak processing temperature along a scan path. A first image may serve to effect spike annealing of the substrates while another may be used to provide auxiliary heat treatment to the substrates before and/or after the spike annealing. Control over the temperature profile of the prespike and/or postspike may also reduce stresses and strains generated in the wafers. Also provided are microelectronic devices formed using the inventive apparatuses and methods.

Abstract: Apparatuses and methods are provide thermally processing of the central portion of a substrate surface using a scanned photonic beam. Such thermal processing is carried out using a shield to block the beam from illuminating the side wall or peripheral portion of the substrate. The shield has characteristics, e.g., diffractive characteristics, effective to maintain the intensity of any unblocked portion of beam suitable for processing the central portion of the substrate surface.

Abstract: Provided are methods for forming an electrically conductive structure of a desired three-dimensional shape on a substantially planar surface of a substrate, e.g., a semiconductor wafer. Typically, the particulate matter is deposited in a layer-by-layer manner and adhered to selected regions on the substrate surface. The particulate matter may be deposited to produce a mold for forming the structure and/or to produce the structure itself. A three-dimensional printer with associated electronic data may be used without the need of a lithographic mask or reticle.

Abstract: Apparatuses and methods are provided for processing a substrate having an upper surface that includes a central region, a peripheral region, and an edge adjacent to the peripheral region. An image having an intensity sufficient to effect thermal processing of the substrate is scanned across the upper surface of the substrate. The image scanning geometry allows processing the central region of the substrate at a substantially uniform temperature without damaging the outer edge. In some instances, the image may be formed from a beam traveling over at least a portion of the central region so that no portion thereof directly illuminates any portion of the edge when the image is scanned across the periphery region. The substrate may be rotated 180° or the beam direction may be switched after part of the scanning operation has been completed.

Abstract: Systems and methods for forming a time-averaged line image having a relatively high amount of intensity uniformity along its length is disclosed. The method includes forming at an image plane a line image having a first amount of intensity non-uniformity in a long-axis direction and forming a secondary image that at least partially overlaps the primary image. The method also includes scanning the secondary image over at least a portion of the primary image and in the long-axis direction according to a scan profile to form a time-average modified line image having a second amount of intensity non-uniformity in the long-axis direction that is less than the first amount. For laser annealing a semiconductor wafer, the amount of line-image overlap for adjacent scans of a wafer scan path is substantially reduced, thereby increasing wafer throughput.

Abstract: Methods and apparatuses are provided for positioning a substrate having a target that may be located on either the front-side or the backside of the substrate. The optical detector that views the target contains a signal-generating material that is substantially identical to the substrate material.