Abstract: A method is provided for forming fluorosilicate glass (FSG) layers that serve as inter-metal dielectric (IMD) layers in a semiconductor wafer with a high moisture-resistant capability. In particular, the method can nonetheless allow the resultant semiconductor circuit to have a low RC delay. The method includes the step of subjecting the FSG layer to a plasma treatment so as to form a moisture-resistant layer over the FSG layer. In the plasma treatment, the ionized gas of ammonia is used as the plasma. As a result of this plasma treatment, a layer of nitrogen-containing compound having a high moisture-resistant property is formed over the FSG layer, which serves as a moisture-resistant layer that can protect the FSG layer from absorbing moistures.

Abstract: A method is described for taking a lifetime measurement of an ultra-thin dielectric layer. In order to discover the life time of the ultra-thin dielectric layer, the measurement comprises using about one half of a stress voltage to measure a time-dependent leakage current of the ultra-thin dielectric layer.

Abstract: A method for fabricating a shallow trench isolation structure is described, in which a pad oxide layer, a silicon oxy-nitride layer and the silicon nitride layer are sequentially formed on the substrate. Photolithography and etching are further conducted to form a trench in the substrate. A liner oxide layer is then formed on the exposed substrate surface in the trench, followed by removing portions of the silicon nitride layer and the silicon oxy-nitride layer by wet etching. After this, the trench is filled with an oxide material d the excessive oxide material is removed by using the silicon nitride layer as barrier layer. The remaining silicon nitride layer and the silicon oxy-nitride layer are further removed to complete the fabrication of a shallow trench isolation structure.

Abstract: A method of manufacturing a two-bit flash memory. A substrate has a thin oxide layer, a silicon nitride layer and a material layer formed thereon in sequence. An opening is formed in the material layer and the silicon nitride layer to expose a portion of the thin oxide layer. A source/drain region is formed in the substrate beneath the portion of the thin oxide layer exposed by the opening. A first dielectric layer is formed in the opening. A portion of the material layer and a portion of the silicon nitride layer are removed to form a spacer on the sidewall of the first dielectric layer. The remaining material layer is removed. A portion of the thin oxide layer exposed by the remaining silicon nitride layer and the first dielectric layer is removed. A second dielectric layer is formed on a portion of the substrate exposed by the remaining thin oxide layer. A control gate is formed over the substrate.

Abstract: A method of fabricating flash erasable programmable read only memory. A substrate having an isolation structure is provided. A tunnel oxide layer and a floating gate layer are formed in sequence over substrate and are patterned. An ion implantation is performed and a first doped region is formed in the substrate. An oxidation step is performed to form a first oxide layer over the substrate. A nitride/oxide layer and a control gate layer are formed in sequence over the substrate. The control gate layer, the nitride/oxide layer, the first oxide layer, and the floating gate layer are patterned until the substrate is exposed. An ion implantation step is performed to form a common source region and a drain region in the substrate. Spacers are formed over the sidewalls of the control gate layer, the nitride/oxide layer, the first oxide layer, and the floating gate layer. A self-aligned silicide step is performed to form silicide layers over the control gate layer, the common source region, and the drain region.

Abstract: A method of fabricating a capacitor. A crown-shape bottom storage node is formed on a conductive region. The crown-shape bottom storage node has a wavelike interior surface and a hemi-spherical grained exterior surface. A dielectric layer is formed on the bottom storage node, and a top electrode is formed to cover the dielectric layer.

Abstract: A method of fabricating a bottom electrode of a capacitor, in which a semiconductor substrate is provided wherein a transistor is formed thereon and the transistor contains a source/drain region. A dielectric layer having a contact hole is formed over the substrate wherein a portion of the source/drain region is exposed by the contact hole. A doped polysilicon layer is formed over the substrate. An insulating layer is formed on the doped polysilicon layer. An amorphous silicon layer is formed on the insulating layer. The amorphous silicon layer, the insulating layer and the doped polysilicon layer are defined to form a main structure of the bottom electrode. Amorphous silicon spacers are formed on sidewalls of the main structure. A hemispherical grained silicon layer is formed on the amorphous silicon layer and the amorphous silicon spacers.

Abstract: A method for manufacturing an even dielectric layer. A substrate having a patterned conductive layer formed thereon is provided. A first dielectric layer with a relatively high dopant dosage is formed on the substrate and the patterned conductive layer. A second dielectric layer with a relatively low dopant dosage is formed on the first dielectric layer. A chemical-mechanical polishing process is formed.

Abstract: A method for forming a stacked capacitor. A gate is formed on a provided substrate. Doped regions are formed in the substrate beside the gate. A first dielectric layer is formed over the substrate. A part of the first dielectric layer is removed to form a node contact opening and a bit line contact opening. The bit line contact opening is located between the gate and separates the gate into two portions. Spacers are formed on sidewalls of the node contact openings and on the bit line contact opening. Conductive material is formed to fill the openings to form a bit line and a landing pad. A second dielectric layer having a opening exposing the landing pad is formed on the first dielectric layer. Conductive material is formed to fill the opening to form a lower electrode. A dielectric film and a upper are formed on the lower electrode.

Abstract: A method for fabricating a passivation layer of a gate electrode. A conductive layer, a mask layer and a patterned photoresist layer are sequentially formed on a gate oxide layer. The photoresists layer is thick enough to precisely transfer a pattern from the photoresist layer to the mask layer. The photoresist layer is stripped, and an etching step is performed to transfer the patterned of the mask layer onto the conductive layer, so as to form a gate electrode. During the etching step, a corner of the mask layer is partly truncated to form a cap layer with an arc shape corner. A conformal liner oxide layer is formed on the cap layer and a sidewall of the gate electrode. A spacer is further formed on the conformal liner oxide layer extending over a top surface of the gate electrode.

Abstract: An improved method of forming a conductive line on a semiconductor substrate is described. A conductive layer is formed on the substrate. A patterned photoresist layer is formed on the conductive layer. A first etching step is performed on the conductive layer to define the conductive layer and to form a conductive line. A second etching step is performed on the conductive line to undercut the conductive line so as to make the conductive line have smaller bottom and to increase a distance between neighboring conductive lines. A third etching step is performed to remove residue generated on the substrate during the first and the second etching steps. A dielectric layer is formed to cover the conductive line. A planarization process is performed.

Abstract: A damascene process, applicable to a semiconductor substrate, with a patterned first mask layer formed thereon. A part of the substrate not covered by the first mask layer is exposed, while a first dielectric layer is formed on the exposed part of the substrate. The first mask is then removed to form a first opening in the first dielectric layer. A conformal barrier layer is formed on the substrate and the first dielectric layer, followed by filling the first opening with a metal plug. Alternatively, a dual damascene process is disclosed where a second patterned mask layer is formed in first opening and covers a part of the first dielectric layer, while a part of the first dielectric layer is exposed. A second dielectric layer is formed on the exposed part of the first dielectric layer. The second patterned mask layer is removed to form a second opening and to expose the first opening.

Abstract: A method of fabricating a semiconductor device is described. A conductive layer is formed on a substrate. A spacer is formed on a sidewall of the conductive layer. A thin metallic layer is formed over the substrate. An ion implantation step is performed. A first seeding layer is formed between the first metallic layer and the conductive layer. A second seeding layer is formed between the first metallic layer and the substrate. A second metallic layer is formed over the substrate. An annealing step is performed to form a self-aligned silicide layer on the conductive layer. The first metallic layer and the second metallic layer that do not react are removed.

Abstract: A method of fabricating a flash memory. A gate is formed on a provided substrate. A first doping process is performed. A patterned mask layer is formed over the substrate. A shallow trench isolation structure is formed in the substrate by using the gate and the mask layer as a mask. A portion of the substrate defined below the gate is a first active region and a portion of the substrate defined below the mask layer is a second active region. The mask layer is removed. A dielectric layer and a conductive layer are formed in sequence over the substrate. The conductive layer, the dielectric layer and the gate are patterned to form a control gate and a floating gate, wherein a portion of the control gate overlap with the second active region. A second doping process is performed.

Abstract: A fully self-aligned method for fabricating a transistor is described. The source/drain contact opening is formed in the forming step of the gate to avoid the problem of misalignment. Therefore, the complex processes and the poly pad layer of the conventional method are not needed. A fully self-aligned method for fabricating memory is described. The memory cell and logic circuit regions have the same height during the formation process of the memory.

Abstract: A method for fabricating a shallow trench isolation (STI) structure includes a pad oxide layer and a hard masking layer are sequentially formed over a semiconductor substrate. A trench is formed in the substrate by patterning over the substrate. Then, the hard masking layer is removed to expose the pad oxide layer. An insulating layer is formed over the substrate to fill the trench. Using the pad oxide layer as a polishing stop, a CMP process is performed to polish the insulating layer until the pad oxide layer is exposed. The remained pad oxide within the trench is simultaneously planarized to have a planar top surface without dishing and microscratch. After the pad oxide is removed, the STI structure is accomplished.

Abstract: A method of fabricating a shallow trench isolation includes formation of a trench in a substrate. A high-density plasma chemical vapor deposition is performed with a plasma which does not contain argon gas. A liner oxide layer is formed on the substrate exposed in the trench. Another high-density plasma chemical vapor deposition is performed. A silicon oxide layer is formed. Then, some follow-up steps are performed to complete the shallow trench isolation.

Abstract: A shallow trench isolation process is described. A pad oxide layer is formed over a substrate. A silicon nitride layer is formed over the pad oxide layer. The silicon nitride layer is patterned. The pad oxide layer and the substrate are etched using the patterned silicon nitride as an etching mask, and thus a trench is formed in the substrate. A liner oxide layer is grown over the trench. An oxide layer is deposited to fill the trench in the substrate and has a surface level higher than the silicon nitride layer. The oxide layer is polished to partially remove the oxide layer over the silicon nitride layer. The silicon nitride layer is removed from the substrate, by which removal the oxide layer has an exposed sidewall. A polysilicon spacer is formed on the exposed sidewall. The pad oxide layer is removed. The polysilicon spacer is oxidized and transformed into an oxide spacer.

Abstract: A method of fabricating a DRAM capacitor. A conductive layer and an amorphous silicon layer are formed on a substrate having a dielectric layer. The amorphous silicon layer and the conductive layer are etched to form a region of a capacitor to expose a portion of the dielectric layer. An opening with a profile having a wider upper portion and a narrower lower portion is formed within the conductive layer, and through the opening, the dielectric layer is then etched through to form a node contact window to expose the substrate. An amorphous silicon spacer is formed on the sidewall of conductive layer of the region of the capacitor and fills the node contact window. A selective HSG-Si, a dielectric layer and a polysilicon layer are formed to achieve the fabrication of the capacitor. The conductive layer, the amorphous silicon layer and the HSG-Si serve as a lower electrode of the capacitor and the polysilicon layer serves as an upper electrode of the capacitor.

Abstract: A method for forming hemispherical silicon grains on selected surfaces of a silicon layer includes the steps of forming a doped polysilicon layer over a substrate, and then forming amorphous spacers on the sidewalls of the doped polysilicon layer. Thereafter, an ion implantation is carried out to transform the upper portion of the doped polysilicon into an amorphous silicon layer. Finally, hemispherical silicon grains are formed on the upper surface of the amorphous layer lying above the polysilicon layer and the exposed surface of the amorphous spacers.