Abstract: The present invention is directed towards a method of fabricating a self-aligned silicide on gate electrode and source/drain region of a semiconductor device. A semiconductor substrate having gate oxide layer and polysilicon layer is provided. Next, a first silicide layer is formed on polysilicon layer. The substrate is patterned and then, etched to form a gate structure. A spacer is formed on the sidewall of the gate structure and source/drain region is formed adjacent thereto. A metal layer is covered on the surface of the substrate. The substrate is performed a thermal process to convert the portion of the metal layer on gate structure and source/drain region into self-aligned silicide.

Abstract: A method of fabricating a dynamic random access memory is described. The surrounding of a capacitor is covered with stop layers to prevent damage during the etching process for forming a bit line contact opening. A first dielectric layer is formed and it is patterned to form a capacitor opening therein. A conformal first stop layer is formed and covers the first dielectric layer and the capacitor opening. A part of the conformal first stop layer on the first source/drain is removed to form a self-aligned node contact opening. The capacitor is formed in the capacitor opening and the self-aligned node contact opening. A conformal second stop layer layer are formed over the substrate. A part of the second dielectric layer over the second source/drain, the conformal second stop layer, the first stop layer and the first dielectric layer underneath is removed to form a self-aligned bit line contact opening. A bit line is formed over the third dielectric layer and within the self-aligned bit line contact opening.

Abstract: A method for processing a poly defect is described. A substrate is provided, and a first oxide layer is formed on the substrate. A polysilicon layer is formed on the first oxide layer, and a poly defect is formed on the polysilicon layer surface simultaneous with polysilicon layer formation. A second oxide layer is formed conformal to the substrate, a portion of the second oxide layer and the poly defect are removed by polishing until a thin second oxide layer and a thin poly defect layer are formed. Finally, the thin second oxide layer is removed.

Abstract: A method for fabricating a flash memory is provided. The method contains sequentially forming a tunnel oxide layer, a first polysilicon layer, and a silicon nitride layer on a semiconductor substrate. A shallow trench isolation (STI) structure is formed in the substrate to define an active area. During the formation of the STI structure, the first polysilicon is simultaneously pre-patterned. The silicon nitride layer is removed. A dielectric layer and a second polysilicon layer are sequentially formed over the substrate. The second polysilicon layer, the dielectric layer, the first polysilicon layer, and the tunnel oxide layer are patterned to form a desired strip structure on the substrate. A remaining portion of the first polysilicon layer serves as a gate of a memory cell. An interchangeable source/drain region is formed by ion implantation at each side of the gate structure, in which a source line parallel to the strip remaining structure.

Abstract: A method of fabricating a high voltage semiconductor device. A semiconductor substrate doped with a first type dopant and comprising a gate is provided. A cap oxide layer is formed on the gate optionally. A first ion implantation with a light second type dopant at a wide angle is performed to form a lightly doped region. A spacer is formed on a side wall of the gate. A second ion implantation with a heavy second type dopant is performed, so that a heavily doped region is formed within the lightly doped region.

Abstract: A method for fabricating a gate structure which has gate dielectric layers of different thicknesses. Since the conducting layer and the protective layer are formed respectively on the dielectric layer after the formation the dielectric layer, the dielectric layer and the photoresist involved in the photolithographic etching are effectively isolated from each other. Also, the dielectric layer is formed by performing oxidation once, so the dielectric layer formed as such has different compositions from that of the dielectric layer formed by double oxidation. Thus, the contamination of the dielectric layer by the photoresist is greatly reduced while the quality and reliability of the dielectric layer are greatly improved.

Abstract: A method of manufacturing a capacitor for a mixed-mode circuit device. A substrate having an isolation region is provided. A bottom electrode is formed on the isolation region. A spacer is formed on a sidewall of the bottom electrode. A dielectric layer is formed on the bottom electrode. A conductive layer is formed over the substrate. The conductive layer is patterned to form an upper electrode.

Abstract: A method of chemical-mechanical polishing. A die region and a scribe line region are defined on a wafer. A dummy pattern is formed in the scribe line region. A dielectric layer is formed to cover the dummy pattern and the wafer. The dielectric layer is planarized by chemical-mechanical polishing.

Abstract: A method for forming a stacked gate of a flash memory cell is described. A first dielectric layer, a conductive layer and a silicon nitride layer are sequentially formed over a substrate. A photoresist pattern is formed over the silicon nitride layer. The silicon nitride layer, conductive layer, first dielectric layer and substrate are etched by using the photoresist pattern as an etching mask until forming a plurality of trenches in the substrate. An insulating layer is formed over the substrate, wherein the insulating layer has a surface level between a top surface of the conductive layer and a bottom surface of the conductive layer. A conductive spacer is formed on the sidewalls of the conductive layer and silicon nitride layer, wherein the conductive spacer and conductive layer serve as a first gate conductive layer. The silicon nitride layer is removed. A second dielectric layer and a second gate conductive layer are formed over the substrate.

Abstract: A method for forming a polysilicon gate electrode. A semiconductor is provided. A gate oxide layer, a partially doped polysilicon layer and an undoped polysilicon are sequentially formed over the semiconductor substrate. The undoped polysilicon layer, the partially doped polysilicon layer and the gate oxide layer are patterned to form a gate electrode.

Abstract: A method is described for forming a hemispherical grained silicon structure. A patterned amorphous silicon layer is formed over a wafer. The amorphous silicon layer is etched by an etching step with a mixed solution including a hydrofluoric solution and an oxidizing agent. A cleaning step is performed with the hydrofluoric solution. An annealing step is performed to form the hemispherical grained silicon structure.

Abstract: An improved method for fabricating DRAM with a thin film transistor can increase reading and writing speed. In this method, a substrate with a transfer transistor, a word line, a bit line and an interlayer dielectric layer is provided. A bit line contact and a terminal contact are formed in the interlayer dielectric layer. The bit line contact couples to the bit line and the terminal contact couples to the transfer transistor. The terminal contact is a T-shaped structure. An oxide layer is formed to cover the interlayer dielectric layer and the terminal contact to expose the bit line contact. A polysilicon layer is formed to cover the oxide layer and the bit line contact. An ion implantation step is performed to form a first doped region and a second doped region in the polysilicon layer. The polysilicon layer is patterned to make the first doped region into a source region and to make the second doped region into a drain region.

Abstract: A method for preventing the formation of recesses in the surface of a borophosphosilicate glass layer comprising the step of first forming a borophosphosilicate glass layer over a substrate, then forming a silicon nitride film having a thickness of about 300.ANG. to 1000.ANG. over the borophosphosilicate glass layer. Next, contact windows are formed, followed by cleaning with an RCA solution. The silicon nitride film provides a protective function preventing the formation of recesses on the borophosphosilicate glass surface. Consequently, no short-circuiting metal bridges caused by metal in the recesses after the deposition of metallic conducting wires are formed.

Abstract: A method of fabricating an interconnect is described in which a conductive layer, an anti-reflection layer and a cover layer are sequentially formed on the substrate to form a conductive plug with its bottom situated in the anti-reflection layer. The cover layer and a portion of the anti-reflection layer and the conductive layer are remove to form an opening exposing the substrate and to define the conductive lining structures. A conformal polysilicon oxide layer is formed on the substrate and a first dielectric layer is also formed, filling the opening. A conformal isolation layer is then formed on the substrate, followed by forming a second dielectric layer covering the entire substrate. A planarization procedure is further conducted to expose the conductive plug.

Abstract: A method for fabricating a capacitor in DRAM. A horizontal buried doped region is formed in a substrate. A pad oxide layer and a mask layer are formed in sequence on the substrate. A plurality of first trenches is formed in the substrate. Thus, a plurality of bit lines is formed in the substrate. A plurality of second trenches is formed in the substrate to expose the surface of the bit lines, wherein the second trenches cross the first trenches. Thus, a plurality of silicon islands on the bit lines is formed. A first insulation layer is formed in the first trenches and the second trenches, wherein the sidewall of the silicon islands are partly exposed and doped regions are formed in the exposed sidewall. A gate oxide layer is formed on the sidewall of the silicon islands. A spacer is formed on the gate oxide layer. A second insulation layer is formed over the substrate. The mask layer and the pad oxide layer are removed to expose the top surfaces of the silicon islands.

Abstract: A method of forming a dynamic random access memory cell such that the gate conductive layer, the bit line contact, the node contact, the bit line and the node contact plug are all formed using self-aligned processes. By employing the self-aligned method of forming DRAM cell, isolation structures are no longer etched in the process of forming the node contact opening. In addition, the aspect ratio of the node contact opening is reduced and processing window is thereby widened.

Abstract: A fabrication method for a dual damascene structure comprising an air-gap is provided. The method includes forming sequentially a first dielectric layer, a stop layer and a second dielectric layer on a substrate comprising a first metal layer. The first and the second dielectric layers are then defined to form a via. opening exposing the first metal layer and an opening in a predetermined position on the first and second dielectric layers. An oxide layer is then formed on the second dielectric layer covering the opening and forming a gap. The oxide layer and the second dielectric layer are then defined to form a trench, which exposes the first metal layer. A second metal layer and a via plug are then formed in the trench and the via. opening, wherein the second metal layer and the first metal layer are electrically connected through the via plug.

Abstract: A flash memory cell. A heavily doped region with the opposite polarity of the drain region is formed between the channel region and the drain region. The heavily doped region is in a bar shape extending towards both the drain and the source regions along a side of the floating gate. Furthermore, the reading operation is performed in reverse by applying a zero voltage to the drain region, and a non-zero voltage to the source region.

Abstract: A method of manufacturing a liner insulating layer for a node contact hole. A substrate having an first insulating layer formed thereon is provided, wherein the first insulating layer has a node contact hole penetrating through the first insulating layer and exposing the substrate. A protective layer is formed on the substrate exposed by the node contact hole. A liner insulating layer is formed on the first insulating layer and in the node contact hole. A second insulating layer is formed on a portion of the liner insulating layer formed on the sidewall of the node contact hole. A portion of the liner insulating layer uncovered by the second insulating layer is removed. The protective layer and the second insulating layer are removed.

Abstract: A retardation layer of a copper damascene process and the fabrication method thereof, to replace the conventional barrier layer with a laminated layer. The laminated layer combines the conventional barrier layer with a porous layer, wherein the porous layer can be formed either above or below the barrier layer to improve the retardation of the copper atom diffusion. Preferably, the porous layer is formed above the barrier layer.