Abstract: An optical transmission device is provided. The optical transmission device is coupled between a first electronic device and a second electronic device, and includes a first optical transceiver module coupled to the first electronic device; a second optical transceiver module coupled to the second electronic device; and first and second optical fibers coupled between the first optical transceiver module and the second optical transceiver module, wherein the second optical transceiver module transmits an optical signal to the first optical transceiver module periodically when the second electronic device is idle for a first predetermined period.

Abstract: A control circuit disposed in a connection line including a first power pin and a second power pin and including a native N-type transistor, a first impedance unit, and a second impedance unit is provided. The native N-type transistor includes a first gate, a first drain and a first source. The first drain is coupled to the first power pin. The first impedance unit is coupled between the first source and the second power pin. The second impedance unit is coupled between the first drain and the first gate. When the voltage level of the first power pin is equal to a pre-determined level, the first gate of the native N-type transistor receives an adjusting signal to adjust an equivalent impedance of the native N-type transistor.

Abstract: An interface chip with a built-in self-test mechanism. An electrical physical layer (EPHY) provides a signal to a transmission terminal of the interface chip, and gets a signal from a reception terminal of the interface chip. A digital code generator generates a source code to be scrambled as a scrambled code and then encoded by an encoder and conveyed to the EPHY to be converted into the signal that is provided to the transmission terminal by the EPHY. The EPHY further converts the signal received from the reception terminal into a receiving code to be decoded by a decoder as a decoded code and then descrambled by the descrambler as a restored code. When the transmission terminal is coupled back to the interface chip via the reception terminal, the code checker checks whether the restored code matches the source code.

Abstract: An operating system including a voltage converter, a processing circuit, and a protector is provided. The voltage converter converts an input voltage according to a feedback voltage to generate an output voltage. The processing circuit is coupled to the voltage converter and processes the output voltage according to a control signal to generate the feedback voltage. The protector is coupled to the voltage converter and the processing circuit and activates or deactivates the voltage converter according to the feedback voltage.

Abstract: A microprocessor includes a plurality of processing cores and a configuration register configured to indicate whether each of the plurality of processing cores is enabled or disabled. Each enabled one of the plurality of processing cores is configured to read the configuration register in a first instance to determine which of the plurality of processing cores is enabled or disabled and generate a respective configuration-related value based on the read of the configuration register in the first instance. The configuration register is updated to indicate that a previously enabled one of the plurality of processing cores is disabled. Each enabled one of the plurality of processing cores is configured to read the configuration register in a second instance to determine which of the plurality of processing cores is enabled or disabled and generate the respective configuration-related value based on the read of the configuration register in the second instance.

Abstract: A probe card including a circuit board, a transformer, a probe head, and a reinforcement structure is provided. The transformer including a body, a plurality of solder balls, and a plurality of first contact points are disposed on the substrate. The body has a first surface and a second surface, wherein the first surface is located between the circuit board and the second surface. The solder balls are disposed on the first surface, and the first contact points are disposed on the second surface. The probe head is disposed on the second surface. The probe head is electrically connected to the circuit board by the first solder balls. The reinforcement structure is disposed between the probe head and the circuit board.

Abstract: A multi-core microprocessor is organized into a plurality of resource-associated domains including core domains, group domains, and a global domain. Each domain relates to either local resources, group resources, or global resources that are respectively used by a single core, a group of cores, or all the cores. Each core has its own independently settable target operating state selected from a plurality of possible target operating states that designate configurations for the local resources, group resources, and global resources. Each core is provided with coordination logic configured to implement or request implementation of the core's target operating state, but only to the extent that implementation of the target operating state would not reduce performance of any other core below its own target operating state.

Abstract: A process for fabricating a circuit substrate is provided. A dielectric layer is formed to cover a surface of a circuit stack and a patterned conductive layer, and has bonding openings exposing bonding segments of traces of the patterned conductive layer, and has plating openings exposing plating segments of the traces. A plating seed layer is formed to cover the surface of the circuit stack, the bonding segments, the plating segments, and the dielectric layer. A mask is formed to cover the plating layer and has mask openings exposing portions of the plating seed layer on the bonding segments. Portions of the plating seed layer on the bonding segments are removed with use of the mask as an etching mask. A thickening conductive layer is plated on each of the bonding segments with use of the mask as a plating mask. The mask and the plating seed layer are removed.

Abstract: A control chip coupled to a first input/output pin and a second input/output pin and including a first interface module, a second interface module, a first switching unit, and a control unit is provided. The first interface module includes a first pin electrically connected to the first input/output pin and a second pin. The second interface module includes a third pin. The control unit controls the first switching unit to turn on a first path between the second pin and the second input/output pin or a second path between the third pin and the second input/output pin. When the first path is turned on, the first interface module controls the voltage levels of the first and second input/output pins. When the second path is turned on, the second interface module controls the voltage level of the second input/output pin.

Abstract: A low-density parity-check (LDPC) apparatus and a matrix trapping set breaking method are provided. The LDPC apparatus includes a logarithm likelihood ratio (LLR) mapping circuit, a variable node (VN) calculation circuit, an adjustment circuit, a check nodes (CN) calculation circuit and a controller. The LLR mapping circuit converts an original codeword into a LLR vector. The VN calculation circuit calculates original V2C information by using the LLR vector and C2V information. The adjustment circuit adjusts the original V2C information to get adjusted V2C information in accordance with a factor. The CN calculation circuit calculates the C2V information by using the adjusted V2C information, and provides the C2V information to the VN calculation circuit. The controller determines whether to adjust the factor. When LDPC iteration operation falls into matrix trap set, the controller decides to adjust the factor so that the iteration operation breaks away from the matrix trap set.

Abstract: An apparatus is provided that compensates for misalignment on a synchronous data bus. The apparatus includes a replica radial distribution element, a Joint Test Action Group (JTAG) interface, and a bit lag control element. The replica radial distribution element is configured to receive a lag pulse signal, and is configured to generate a replicated strobe signal, where the replica radial distribution network includes replicated propagation path lengths, loads, and buffering of a radial distribution network for a strobe. The JTAG interface is configured to receive control information over a standard JTAG bus, where the control information indicates an amount to adjust a propagation time. The bit lag control element is configured to measure, when an update signal is asserted, the propagation time beginning with assertion of the first signal and ending with assertion of the second signal, and is configured to generate a first value on a lag bus that indicates an adjusted propagation time.

Abstract: An apparatus is provided that compensates for misalignment on a synchronous data bus, the apparatus includes a replica radial distribution element, a bit lag control element, and a synchronous lag receiver. The replica radial distribution element is configured to receive a lag pulse signal, and is configured to generate a replicated strobe signal, where the replica radial distribution network includes replicated propagation path lengths, loads, and buffering of a radial distribution network for a strobe. The bit lag control element is configured to measure the time between assertion of the lag pulse signal and assertion of the replicated strobe signal, and is configured to generate a first value on a lag bus that indicates the time.

Abstract: A non-volatile memory apparatus includes an error checking and correcting (ECC) decoding circuit, a main buffer circuit, a multiplexer, and an interface circuit. The ECC decoding circuit decodes an original codeword to obtain a decoded codeword. The main buffer circuit is coupled to the ECC decoding circuit for receiving and storing a first data portion of the decoded codeword. The multiplexer's first input end is coupled to the output end of the main buffer circuit. The second input end of the multiplexer is coupled to the output end of the ECC decoding circuit. The interface circuit is coupled to the output end of the multiplexer and receives the first data portion from the multiplexer to provide the first data portion to a host.

Abstract: A method is provided for managing power consumption within a multi-core microprocessor. An operating system issues an operating system instruction to transition a recipient core to a targeted power and/or performance state that is one of many possible states into which a microprocessor can place a core. Each core of the microprocessor has its own target state, and different cores may have different target states. After receiving the instruction, the recipient core implements any settings associated with its target core state that wouldn't affect resources shared with other cores. The recipient core also initiates an inter-core discovery process to determine a target multi-core state of all the cores sharing the resource. The target multi-core state reflects one or more settings that match the settings of the recipient core's target core state as much as possible without lowering a performance of any resource-sharing core below that core's own target core state.

Abstract: A memory chip coupled to a host includes a memory and a controller. The memory is pre-loaded with a plurality of boot images, wherein the boot images have the same content. The controller is coupled to the memory, and processes data transmissions between the memory chip and the host, wherein the controller further determines whether the memory chip enters a boot mode for the first time, and when the memory chip enters the boot mode for the first time, the controller accesses the memory to obtain a correct boot image from the boot images and transmits the correct boot image to the host. Further, each boot image includes a plurality of data blocks, and the controller loads a plurality of correct data blocks from one or more of the boot images to obtain the correct boot image.

Abstract: A probe card including a circuit board, a transformer, a probe head, and a reinforcement structure is provided. The transformer including a body, a plurality of solder balls, and a plurality of first contact points are disposed on the substrate. The body has a first surface and a second surface, wherein the first surface is located between the circuit board and the second surface. The solder balls are disposed on the first surface, and the first contact points are disposed on the second surface. The probe head is disposed on the second surface. The probe head is electrically connected to the circuit board by the first solder balls. The reinforcement structure is disposed between the probe head and the circuit board.

Abstract: A system, a control apparatus and a control method for distributed video display are provided. The system includes an image source device configured to provide image data, a plurality of displays, a plurality of display chips respectively coupled to the displays and connected with the video source device through a network, and a control apparatus connected with the image source device and the display chips through the network and configured to transmit a playback signal to each of the display chips to control the display chips to receive the image data from the image source device and convert the received image data into display frames capable of being played by the displays.

Abstract: A microprocessor includes a plurality of cores, a shared cache memory, and a control unit that individually puts each core to sleep by stopping its clock signal. Each core executes a sleep instruction and responsively makes a respective request of the control unit to put the core to sleep, which the control unit responsively does, and detects when all the cores have made the respective request and responsively wakes up only the last requesting cores. The last core writes back and invalidates the shared cache memory and indicates it has been invalidated and makes a request to the control unit to put the last core back to sleep. The control unit puts the last core back to sleep and continuously keeps the other cores asleep while the last core writes back and invalidates the shared cache memory, indicates the shared cache memory was invalidated, and is put back to sleep.

Abstract: A non-volatile memory apparatus including a non-volatile storage circuit, a main memory and a controller, and an operating method thereof are provided. Each of a plurality of logical block address groups includes a plurality of logical block addresses. Each of the logical block address groups is assigned a group read-count value. An adjustment of the group read-count values is triggered by a read command of a host. When one read-count value of the group read-count values exceeds a preset range, the controller performs a scan operation to non-volatile storage blocks of the non-volatile storage circuit corresponding to a corresponding logical block address group of the read-count value, so as to check a number of error bits. The controller decides whether to perform a storage block data-moving operation to the non-volatile storage block corresponding to the corresponding logical block address group based on results of the scan operation.