Abstract: A non-volatile memory apparatus including a non-volatile storage circuit, a main memory and a controller, and an operating method thereof are provided. Each of a plurality of logical block address groups includes a plurality of logical block addresses. Each of the logical block address groups is assigned with a group age parameter. The adjusting of the group age parameters is triggered by a writing instruction of a host. When an age parameter of the group age parameters exceeds a predetermined range, the controller performs a scanning operation to the non-volatile storage blocks of the non-volatile storage circuit corresponding to a corresponding logical block address group of the age parameter, so as to check an error-bit quantity. The controller decides whether the storage block data-moving operation is performed to the non-volatile storage block corresponding to the corresponding logical block address group based on the results of the scanning operation.

Abstract: A start-up apparatus for a battery management circuit and a battery management system having the same are provided. The start-up apparatus for the battery management circuit includes a transformer, a switch circuit, a control circuit, and a rectifier circuit. The transformer includes a primary winding, an auxiliary winding, and a secondary winding. A first terminal of the primary winding is coupled to a first external power path. A first terminal of the switch circuit is coupled to a second terminal of the primary winding, and a second terminal of the switch circuit is coupled to a second external power path. The control circuit is coupled to the auxiliary winding for receiving power and controls a conduction state of the switch circuit. The rectifier circuit is coupled to the secondary winding of the transformer and supplies power to the battery management circuit.

Abstract: A probe card including a circuit board, a transformer, a probe head, and a reinforcement structure is provided. The transformer including a body, a plurality of solder balls, and a plurality of first contact points are disposed on the substrate. The body has a first surface and a second surface, wherein the first surface is located between the circuit board and the second surface. The solder balls are disposed on the first surface, and the first contact points are disposed on the second surface. The probe head is disposed on the second surface. The probe head is electrically connected to the circuit board by the first solder balls. The reinforcement structure is disposed between the probe head and the circuit board.

Abstract: A natural language recognizing apparatus including an input device, a processing device and a storage device is provided. The input device is configured to provide a natural language data. The storage device is configured to store a plurality of program modules. The program modules include a grammar analysis module. The processing device executes the grammar analysis module to analyze the natural language data through a formal grammar model, and generate a plurality of string data. When at least one of the string data conforms to a preset grammar condition, the processing device judges the at least one of the string data is an intention data, and the processing device outputs a corresponding response signal according to the intention data. In addition, a natural language recognizing method is also provided.

Abstract: A charger and a power delivery control chip and a charging method thereof are provided. Resistance values of equivalent resistances corresponding to a power supply bus are calculated according to a charging current and voltage sensing signals respectively provided by chips of a first connector and a second connector. A charging voltage supplied to the power supply bus is adjusted according to a target charging voltage, a current charging current, and variations of the resistance values of the equivalent resistances corresponding to the power supply bus.

Abstract: An error checking and correcting (ECC) decoding method and apparatus are provided. A decoding circuit decodes a codeword using (or without using) reference information, wherein when the decoding circuit fails to decode a first codeword, the decoding circuit decodes a second codeword to produce decoded data. The decoding circuit checks whether a change has occurred from each codeword bit of the second codeword to a corresponding bit of the decoded data. In accordance with a bit position of the changed corresponding bit, the decoding circuit correspondingly changes the first codeword to a modified codeword, and/or correspondingly changes the reference information to modified information. The decoding circuit performs the ECC decoding again on the modified codeword (or the first codeword) using (or without using) the modified information.

Abstract: A method for using voiceprint identification to operate voice recognition and electronic device thereof are provided. The method includes the following steps: receiving a specific voice fragment; cutting the received specific voice fragment into a plurality of specific sub-voice clips; performing a voiceprint identification flow to the specific sub-voice clips, respectively; determining whether each of the specific sub-voice clips is an appropriate sub-voice clip according to a result of the voiceprint identification flow; and capturing the appropriate sub-voice clips and operating a voice recognition thereto.

Abstract: A memory apparatus and an energy-saving control method thereof are provided. The internal clock signal sent to a specific circuit group is stopped outputting when it is determined that no processing command is to be processed currently and current events are finished being processed, so as to reduce power consumption of a control chip.

Abstract: A memory apparatus and an energy-saving control method thereof are provided. The memory apparatus includes a plurality of non-volatile memory units and a control chip, and the control chip includes a specific circuit group, a memory control unit and an energy-saving control unit. The memory control unit controls an access to the non-volatile memory units. In a normal mode and during a period of accessing the non-volatile memory units by the control chip, if the non-volatile memory units are in a busy state, the energy-saving control unit controls the clock generation unit to stop outputting an internal clock signal to the specific circuit group, so as to reduce power consumption of the control chip.

Abstract: A universal serial bus and a control method thereof are provided. Different voltages are respectively provided to circuit groups when a universal serial bus hub is in a suspend state and a normal working state, so as to reduce leakage current.

Abstract: A compressing instruction queue for a microprocessor including a storage queue and a redirect logic circuit. The storage queue includes a matrix of storage locations including N rows and M columns for storing microinstructions of the microprocessor in sequential order. The redirect logic circuit is configured to receive and write multiple microinstructions per cycle of a clock signal into sequential storage locations of the storage queue without leaving unused storage locations and beginning at a first available storage location in the storage queue. The redirect logic circuit performs redirection and compression to eliminate empty locations or holes in the storage queue and to reduce the number of write ports interfaced with each storage location of the storage queue.

Abstract: A paddle card includes a circuit board, a pad group and first to fourth shielding planes. The circuit board has an upper surface and a lower surface opposite to each other. The pad group is adapted to connect wires of a cable or terminals of a plug, and includes a pair of upper differential pads on the upper surface and a pair of lower differential pads on the lower surface. The pair of upper differential pads is respectively configured corresponding to the pair of lower differential pads in an up and down manner. The first to fourth shielding planes are stacked at intervals between the upper and lower surfaces in sequence. An orthogonal projection of a second opening of the second shielding plane on a geometric plane that a pair of third openings of the third shielding plane is located in is separate from the pair of third openings.

Abstract: A method and an apparatus for generating 3D panoramic video are provided. In the method, plural frames are captured from a panoramic video. Each frame is transformed into a polyhedral mapping projection comprising side planes, a top plane and a bottom plane. Displacements of pixels in the side planes are calculated by using the side planes of each frame, and displacements of pixels in the top plane and the bottom plane are calculated by using the displacements of the side planes. Then, the pixels in the side planes, the top plane and the bottom plane of each frame are shifted according the displacements of the polyhedral mapping projection to generate a shifted polyhedral mapping projection. The shifted polyhedral mapping projection is transformed into a shifted frame with 2D space format. The shifted frames and corresponding frames construct 3D images and the 3D images are encoded into a 3D panoramic video.

Abstract: An operating system including a voltage converter, a processing circuit, and a protector is provided. The voltage converter converts an input voltage according to a feedback voltage to generate an output voltage. The processing circuit is coupled to the voltage converter and processes the output voltage according to a control signal to generate the feedback voltage. The protector is coupled to the voltage converter and the processing circuit and activates or deactivates the voltage converter according to the feedback voltage.

Abstract: An interface chip with a built-in self-test mechanism. An electrical physical layer (EPHY) provides a signal to a transmission terminal of the interface chip, and gets a signal from a reception terminal of the interface chip. A digital code generator generates a source code to be scrambled as a scrambled code and then encoded by an encoder and conveyed to the EPHY to be converted into the signal that is provided to the transmission terminal by the EPHY. The EPHY further converts the signal received from the reception terminal into a receiving code to be decoded by a decoder as a decoded code and then descrambled by the descrambler as a restored code. When the transmission terminal is coupled back to the interface chip via the reception terminal, the code checker checks whether the restored code matches the source code.

Abstract: A control circuit disposed in a connection line including a first power pin and a second power pin and including a native N-type transistor, a first impedance unit, and a second impedance unit is provided. The native N-type transistor includes a first gate, a first drain and a first source. The first drain is coupled to the first power pin. The first impedance unit is coupled between the first source and the second power pin. The second impedance unit is coupled between the first drain and the first gate. When the voltage level of the first power pin is equal to a pre-determined level, the first gate of the native N-type transistor receives an adjusting signal to adjust an equivalent impedance of the native N-type transistor.

Abstract: An optical transmission device is provided. The optical transmission device is coupled between a first electronic device and a second electronic device, and includes a first optical transceiver module coupled to the first electronic device; a second optical transceiver module coupled to the second electronic device; and first and second optical fibers coupled between the first optical transceiver module and the second optical transceiver module, wherein the second optical transceiver module transmits an optical signal to the first optical transceiver module periodically when the second electronic device is idle for a first predetermined period.

Abstract: A microprocessor includes a plurality of processing cores and a configuration register configured to indicate whether each of the plurality of processing cores is enabled or disabled. Each enabled one of the plurality of processing cores is configured to read the configuration register in a first instance to determine which of the plurality of processing cores is enabled or disabled and generate a respective configuration-related value based on the read of the configuration register in the first instance. The configuration register is updated to indicate that a previously enabled one of the plurality of processing cores is disabled. Each enabled one of the plurality of processing cores is configured to read the configuration register in a second instance to determine which of the plurality of processing cores is enabled or disabled and generate the respective configuration-related value based on the read of the configuration register in the second instance.

Abstract: A probe card including a circuit board, a transformer, a probe head, and a reinforcement structure is provided. The transformer including a body, a plurality of solder balls, and a plurality of first contact points are disposed on the substrate. The body has a first surface and a second surface, wherein the first surface is located between the circuit board and the second surface. The solder balls are disposed on the first surface, and the first contact points are disposed on the second surface. The probe head is disposed on the second surface. The probe head is electrically connected to the circuit board by the first solder balls. The reinforcement structure is disposed between the probe head and the circuit board.