Patents Assigned to VIA Technologies, Inc.
  • Patent number: 10223017
    Abstract: A memory apparatus and an energy-saving control method thereof are provided. The internal clock signal sent to a specific circuit group is stopped outputting when it is determined that no processing command is to be processed currently and current events are finished being processed, so as to reduce power consumption of a control chip.
    Type: Grant
    Filed: June 27, 2016
    Date of Patent: March 5, 2019
    Assignee: VIA Technologies, Inc.
    Inventors: Yi-Lin Lai, Chen-Te Chen
  • Patent number: 10224029
    Abstract: A method for using voiceprint identification to operate voice recognition and electronic device thereof are provided. The method includes the following steps: receiving a specific voice fragment; cutting the received specific voice fragment into a plurality of specific sub-voice clips; performing a voiceprint identification flow to the specific sub-voice clips, respectively; determining whether each of the specific sub-voice clips is an appropriate sub-voice clip according to a result of the voiceprint identification flow; and capturing the appropriate sub-voice clips and operating a voice recognition thereto.
    Type: Grant
    Filed: April 9, 2014
    Date of Patent: March 5, 2019
    Assignee: VIA TECHNOLOGIES, INC.
    Inventor: Guo-Feng Zhang
  • Patent number: 10216520
    Abstract: A compressing instruction queue for a microprocessor including a storage queue and a redirect logic circuit. The storage queue includes a matrix of storage locations including N rows and M columns for storing microinstructions of the microprocessor in sequential order. The redirect logic circuit is configured to receive and write multiple microinstructions per cycle of a clock signal into sequential storage locations of the storage queue without leaving unused storage locations and beginning at a first available storage location in the storage queue. The redirect logic circuit performs redirection and compression to eliminate empty locations or holes in the storage queue and to reduce the number of write ports interfaced with each storage location of the storage queue.
    Type: Grant
    Filed: December 12, 2014
    Date of Patent: February 26, 2019
    Assignee: VIA TECHNOLOGIES, INC.
    Inventors: Matthew Daniel Day, G. Glenn Henry, Terry Parks
  • Patent number: 10216250
    Abstract: A memory apparatus and an energy-saving control method thereof are provided. The memory apparatus includes a plurality of non-volatile memory units and a control chip, and the control chip includes a specific circuit group, a memory control unit and an energy-saving control unit. The memory control unit controls an access to the non-volatile memory units. In a normal mode and during a period of accessing the non-volatile memory units by the control chip, if the non-volatile memory units are in a busy state, the energy-saving control unit controls the clock generation unit to stop outputting an internal clock signal to the specific circuit group, so as to reduce power consumption of the control chip.
    Type: Grant
    Filed: June 27, 2016
    Date of Patent: February 26, 2019
    Assignee: VIA Technologies, Inc.
    Inventors: Yi-Lin Lai, Chen-Te Chen
  • Patent number: 10218127
    Abstract: A paddle card includes a circuit board, a pad group and first to fourth shielding planes. The circuit board has an upper surface and a lower surface opposite to each other. The pad group is adapted to connect wires of a cable or terminals of a plug, and includes a pair of upper differential pads on the upper surface and a pair of lower differential pads on the lower surface. The pair of upper differential pads is respectively configured corresponding to the pair of lower differential pads in an up and down manner. The first to fourth shielding planes are stacked at intervals between the upper and lower surfaces in sequence. An orthogonal projection of a second opening of the second shielding plane on a geometric plane that a pair of third openings of the third shielding plane is located in is separate from the pair of third openings.
    Type: Grant
    Filed: July 3, 2017
    Date of Patent: February 26, 2019
    Assignee: VIA Technologies, Inc.
    Inventor: Sheng-Yuan Lee
  • Patent number: 10216253
    Abstract: A universal serial bus and a control method thereof are provided. Different voltages are respectively provided to circuit groups when a universal serial bus hub is in a suspend state and a normal working state, so as to reduce leakage current.
    Type: Grant
    Filed: December 23, 2013
    Date of Patent: February 26, 2019
    Assignee: VIA Technologies, Inc.
    Inventors: Yi-Te Chen, Terrance Shiyang Shih, Hsiao-Chyi Lin
  • Publication number: 20190057487
    Abstract: A method and an apparatus for generating 3D panoramic video are provided. In the method, plural frames are captured from a panoramic video. Each frame is transformed into a polyhedral mapping projection comprising side planes, a top plane and a bottom plane. Displacements of pixels in the side planes are calculated by using the side planes of each frame, and displacements of pixels in the top plane and the bottom plane are calculated by using the displacements of the side planes. Then, the pixels in the side planes, the top plane and the bottom plane of each frame are shifted according the displacements of the polyhedral mapping projection to generate a shifted polyhedral mapping projection. The shifted polyhedral mapping projection is transformed into a shifted frame with 2D space format. The shifted frames and corresponding frames construct 3D images and the 3D images are encoded into a 3D panoramic video.
    Type: Application
    Filed: June 13, 2018
    Publication date: February 21, 2019
    Applicant: VIA Technologies, Inc.
    Inventor: Robin J. Cheng
  • Patent number: 10211924
    Abstract: An optical transmission device is provided. The optical transmission device is coupled between a first electronic device and a second electronic device, and includes a first optical transceiver module coupled to the first electronic device; a second optical transceiver module coupled to the second electronic device; and first and second optical fibers coupled between the first optical transceiver module and the second optical transceiver module, wherein the second optical transceiver module transmits an optical signal to the first optical transceiver module periodically when the second electronic device is idle for a first predetermined period.
    Type: Grant
    Filed: January 8, 2015
    Date of Patent: February 19, 2019
    Assignee: VIA TECHNOLOGIES, INC.
    Inventors: Cheng-Ming Ying, Yu-Lung Lin
  • Patent number: 10209756
    Abstract: An operating system including a voltage converter, a processing circuit, and a protector is provided. The voltage converter converts an input voltage according to a feedback voltage to generate an output voltage. The processing circuit is coupled to the voltage converter and processes the output voltage according to a control signal to generate the feedback voltage. The protector is coupled to the voltage converter and the processing circuit and activates or deactivates the voltage converter according to the feedback voltage.
    Type: Grant
    Filed: October 6, 2016
    Date of Patent: February 19, 2019
    Assignee: VIA TECHNOLOGIES, INC.
    Inventors: Wei-Hung Chen, Kuo-Yu Wu
  • Patent number: 10209302
    Abstract: An interface chip with a built-in self-test mechanism. An electrical physical layer (EPHY) provides a signal to a transmission terminal of the interface chip, and gets a signal from a reception terminal of the interface chip. A digital code generator generates a source code to be scrambled as a scrambled code and then encoded by an encoder and conveyed to the EPHY to be converted into the signal that is provided to the transmission terminal by the EPHY. The EPHY further converts the signal received from the reception terminal into a receiving code to be decoded by a decoder as a decoded code and then descrambled by the descrambler as a restored code. When the transmission terminal is coupled back to the interface chip via the reception terminal, the code checker checks whether the restored code matches the source code.
    Type: Grant
    Filed: January 6, 2016
    Date of Patent: February 19, 2019
    Assignee: VIA TECHNOLOGIES, INC.
    Inventors: Yu-Lung Lin, Po-Chou Lin
  • Patent number: 10211813
    Abstract: A control circuit disposed in a connection line including a first power pin and a second power pin and including a native N-type transistor, a first impedance unit, and a second impedance unit is provided. The native N-type transistor includes a first gate, a first drain and a first source. The first drain is coupled to the first power pin. The first impedance unit is coupled between the first source and the second power pin. The second impedance unit is coupled between the first drain and the first gate. When the voltage level of the first power pin is equal to a pre-determined level, the first gate of the native N-type transistor receives an adjusting signal to adjust an equivalent impedance of the native N-type transistor.
    Type: Grant
    Filed: December 21, 2015
    Date of Patent: February 19, 2019
    Assignee: VIA TECHNOLOGIES, INC.
    Inventor: Cheng-Chun Yeh
  • Patent number: 10198269
    Abstract: A microprocessor includes a plurality of processing cores and a configuration register configured to indicate whether each of the plurality of processing cores is enabled or disabled. Each enabled one of the plurality of processing cores is configured to read the configuration register in a first instance to determine which of the plurality of processing cores is enabled or disabled and generate a respective configuration-related value based on the read of the configuration register in the first instance. The configuration register is updated to indicate that a previously enabled one of the plurality of processing cores is disabled. Each enabled one of the plurality of processing cores is configured to read the configuration register in a second instance to determine which of the plurality of processing cores is enabled or disabled and generate the respective configuration-related value based on the read of the configuration register in the second instance.
    Type: Grant
    Filed: May 19, 2014
    Date of Patent: February 5, 2019
    Assignee: VIA TECHNOLOGIES, INC.
    Inventors: G. Glenn Henry, Terry Parks, Darius D. Gaskins
  • Patent number: 10184956
    Abstract: A probe card including a circuit board, a transformer, a probe head, and a reinforcement structure is provided. The transformer including a body, a plurality of solder balls, and a plurality of first contact points are disposed on the substrate. The body has a first surface and a second surface, wherein the first surface is located between the circuit board and the second surface. The solder balls are disposed on the first surface, and the first contact points are disposed on the second surface. The probe head is disposed on the second surface. The probe head is electrically connected to the circuit board by the first solder balls. The reinforcement structure is disposed between the probe head and the circuit board.
    Type: Grant
    Filed: May 21, 2018
    Date of Patent: January 22, 2019
    Assignee: VIA Technologies, Inc.
    Inventors: Chen-Yueh Kung, Wen-Yuan Chang, Wei-Cheng Chen
  • Patent number: 10175732
    Abstract: A multi-core microprocessor is organized into a plurality of resource-associated domains including core domains, group domains, and a global domain. Each domain relates to either local resources, group resources, or global resources that are respectively used by a single core, a group of cores, or all the cores. Each core has its own independently settable target operating state selected from a plurality of possible target operating states that designate configurations for the local resources, group resources, and global resources. Each core is provided with coordination logic configured to implement or request implementation of the core's target operating state, but only to the extent that implementation of the target operating state would not reduce performance of any other core below its own target operating state.
    Type: Grant
    Filed: December 28, 2015
    Date of Patent: January 8, 2019
    Assignee: VIA TECHNOLOGIES, INC.
    Inventors: G. Glenn Henry, Darius D. Gaskins
  • Publication number: 20190006302
    Abstract: A process for fabricating a circuit substrate is provided. A dielectric layer is formed to cover a surface of a circuit stack and a patterned conductive layer, and has bonding openings exposing bonding segments of traces of the patterned conductive layer, and has plating openings exposing plating segments of the traces. A plating seed layer is formed to cover the surface of the circuit stack, the bonding segments, the plating segments, and the dielectric layer. A mask is formed to cover the plating layer and has mask openings exposing portions of the plating seed layer on the bonding segments. Portions of the plating seed layer on the bonding segments are removed with use of the mask as an etching mask. A thickening conductive layer is plated on each of the bonding segments with use of the mask as a plating mask. The mask and the plating seed layer are removed.
    Type: Application
    Filed: September 5, 2018
    Publication date: January 3, 2019
    Applicant: VIA Technologies, Inc.
    Inventor: Chen-Yueh Kung
  • Patent number: 10153759
    Abstract: A control chip coupled to a first input/output pin and a second input/output pin and including a first interface module, a second interface module, a first switching unit, and a control unit is provided. The first interface module includes a first pin electrically connected to the first input/output pin and a second pin. The second interface module includes a third pin. The control unit controls the first switching unit to turn on a first path between the second pin and the second input/output pin or a second path between the third pin and the second input/output pin. When the first path is turned on, the first interface module controls the voltage levels of the first and second input/output pins. When the second path is turned on, the second interface module controls the voltage level of the second input/output pin.
    Type: Grant
    Filed: October 7, 2015
    Date of Patent: December 11, 2018
    Assignee: VIA TECHNOLOGIES, INC.
    Inventors: Hao-Hsuan Chiu, Yen-Ting Lai
  • Patent number: 10141953
    Abstract: A low-density parity-check (LDPC) apparatus and a matrix trapping set breaking method are provided. The LDPC apparatus includes a logarithm likelihood ratio (LLR) mapping circuit, a variable node (VN) calculation circuit, an adjustment circuit, a check nodes (CN) calculation circuit and a controller. The LLR mapping circuit converts an original codeword into a LLR vector. The VN calculation circuit calculates original V2C information by using the LLR vector and C2V information. The adjustment circuit adjusts the original V2C information to get adjusted V2C information in accordance with a factor. The CN calculation circuit calculates the C2V information by using the adjusted V2C information, and provides the C2V information to the VN calculation circuit. The controller determines whether to adjust the factor. When LDPC iteration operation falls into matrix trap set, the controller decides to adjust the factor so that the iteration operation breaks away from the matrix trap set.
    Type: Grant
    Filed: December 14, 2016
    Date of Patent: November 27, 2018
    Assignee: VIA Technologies, Inc.
    Inventors: Ying Yu Tai, Jiangli Zhu
  • Patent number: 10133701
    Abstract: An apparatus is provided that compensates for misalignment on a synchronous data bus. The apparatus includes a replica radial distribution element, a Joint Test Action Group (JTAG) interface, and a bit lag control element. The replica radial distribution element is configured to receive a lag pulse signal, and is configured to generate a replicated strobe signal, where the replica radial distribution network includes replicated propagation path lengths, loads, and buffering of a radial distribution network for a strobe. The JTAG interface is configured to receive control information over a standard JTAG bus, where the control information indicates an amount to adjust a propagation time. The bit lag control element is configured to measure, when an update signal is asserted, the propagation time beginning with assertion of the first signal and ending with assertion of the second signal, and is configured to generate a first value on a lag bus that indicates an adjusted propagation time.
    Type: Grant
    Filed: December 23, 2016
    Date of Patent: November 20, 2018
    Assignee: VIA TECHNOLOGIES, INC.
    Inventors: Vanessa Canac, James R. Lundberg
  • Patent number: 10133700
    Abstract: An apparatus is provided that compensates for misalignment on a synchronous data bus, the apparatus includes a replica radial distribution element, a bit lag control element, and a synchronous lag receiver. The replica radial distribution element is configured to receive a lag pulse signal, and is configured to generate a replicated strobe signal, where the replica radial distribution network includes replicated propagation path lengths, loads, and buffering of a radial distribution network for a strobe. The bit lag control element is configured to measure the time between assertion of the lag pulse signal and assertion of the replicated strobe signal, and is configured to generate a first value on a lag bus that indicates the time.
    Type: Grant
    Filed: December 23, 2016
    Date of Patent: November 20, 2018
    Assignee: VIA TECHNOLOGIES, INC.
    Inventors: Vanessa Canac, James R. Lundberg
  • Patent number: D834634
    Type: Grant
    Filed: March 2, 2017
    Date of Patent: November 27, 2018
    Assignee: VIA TECHNOLOGIES, INC.
    Inventor: Chih-Wei Huang