Patents Assigned to VIA Technologies, Inc.
  • Patent number: 11334429
    Abstract: A non-volatile memory apparatus includes an error checking and correcting (ECC) decoding circuit, a first cyclic redundancy check (CRC) circuit, a second CRC circuit, and an interface circuit. The ECC decoding circuit decodes an original codeword to obtain a decoded codeword. The interface circuit receives and provides a first data portion of the decoded codeword to a host. The first CRC circuit performs a first CRC on the first data portion and generates a check status message based on a relationship between a result of the first CRC and a first CRC code of the decoded codeword. The second CRC circuit performs a second CRC on the first data portion to generate a second CRC code. The second CRC circuit determines whether to further change the second CRC code to make the second CRC code not match the first data portion according to the check status message.
    Type: Grant
    Filed: August 5, 2020
    Date of Patent: May 17, 2022
    Assignee: VIA Technologies, Inc.
    Inventors: Yi-Lin Lai, Chen-Te Chen, Ying-Che Chung
  • Patent number: 11249894
    Abstract: A storage device includes a flash memory array and a controller. The flash memory array includes a plurality of blocks. A minimal erase number of blocks have a minimal erase count in the plurality of blocks. When one of the minimal erase number of blocks is erased, the controller subtracts 1 from the minimal erase number.
    Type: Grant
    Filed: June 13, 2018
    Date of Patent: February 15, 2022
    Assignee: VIA TECHNOLOGIES, INC.
    Inventors: Zhongyi Gao, Xiaoyu Yang
  • Patent number: 11216648
    Abstract: A method for facial image recognition is provided. A plurality of original facial images are received. A plurality of standard facial images corresponding to the original facial images are generated through a standard face generation model. A recognition model is trained by using the original facial images and the standard facial images. The recognition model is tested by using the original facial image test set and a standard facial image test set until the recognition model recognizes that the first accuracy rate of the original facial image test set is higher than a first threshold value and the second accuracy rate of the standard facial image test set is higher than a second threshold value. The original facial image test set is composed of the original facial images obtained by sampling, and the standard facial image test set is composed of the standard facial images obtained by sampling.
    Type: Grant
    Filed: March 3, 2020
    Date of Patent: January 4, 2022
    Assignee: VIA TECHNOLOGIES, INC.
    Inventor: Hao Sun
  • Publication number: 20210320800
    Abstract: An authorization method and an authorization system are provided. The authorization method includes displaying, by a service device, authorization information on an e-paper arranged on the service device; obtaining, by a user device, the authorization information from the e-paper; and using, by the user device, the authorization information displayed on the e-paper to perform an authorization operation between the user device and the service device.
    Type: Application
    Filed: July 31, 2020
    Publication date: October 14, 2021
    Applicant: VIA Technologies, Inc.
    Inventor: Yaozhong XU
  • Publication number: 20210303193
    Abstract: A data storage system and a global deduplication method thereof are provided. The data storage system includes multiple storage devices and one dispatch device. The dispatch device divides an original data corresponding to a data writing request into at least one data chunk. The dispatch device performs a summary calculation on one data chunk, so as to generate a representative value. The dispatch device performs a first distribution calculation on the representative value, so as to determine a destination location corresponding to the representative value. The dispatch device transmits the data chunk and the representative value to at least one destination storage device among the storage devices through a communication network according to the destination location. The at least one destination storage device checks the representative value, so as to determine whether to store the data chunk in a storage space of the at least one destination storage device.
    Type: Application
    Filed: March 8, 2021
    Publication date: September 30, 2021
    Applicant: VIA Technologies, Inc.
    Inventors: Chin-Yin Tsai, Yi-Lin Lai
  • Patent number: 11126544
    Abstract: A non-volatile memory (NVM) apparatus and a garbage collection method thereof are provided. The NVM apparatus includes a NVM and a controller. The controller is coupled to the NVM. The controller accesses the NVM according to a logical address of a write command of a host. The controller performs the garbage collection method to release space occupied by invalid data. The garbage collection method includes: grouping a plurality of blocks of the NVM into a plurality of tiers according to hotness of data, moving valid data in one closed source block of a hotter tier among the tiers to one open target block of a cooler tier among the tiers, and erasing the closed source block of the hotter tier to release space.
    Type: Grant
    Filed: December 14, 2016
    Date of Patent: September 21, 2021
    Assignee: VIA Technologies, Inc.
    Inventors: Ying Yu Tai, Jiangli Zhu
  • Patent number: 11093529
    Abstract: A method for displaying landmark data from a search of a place name keyword, the method includes: inputting the place name keyword to a server to search for a plurality of landmark data, wherein each of the landmark data comprises fields of a landmark name, an objective level category, an address, and an address quoting frequency; sorting the landmark data by an electronic device to a display order, based on a characterized parameter for each of the landmark, wherein the characterized parameter is calculated based on at least a publicity, wherein the publicity is a calculation of the objective level category and the address quoting frequency with respectively weighting to the objective level category and the address quoting frequency; and displaying the landmark data by the electronic device according to the display order.
    Type: Grant
    Filed: March 28, 2018
    Date of Patent: August 17, 2021
    Assignee: VIA Technologies, Inc.
    Inventors: Guo-Feng Zhang, Yi-Fei Zhu
  • Patent number: 11010312
    Abstract: A security system and a security method of stored data are provided. In the security system and the security method, a central processing unit performs hashing operation on a seed code to generate a data access code, which is then compared with a password stored in a storage device. If there is no password in the storage device, the data access code is written into the storage device as the password. On the other hand, if the data access code does not match the password, the storage device denies the access request from the central processing unit.
    Type: Grant
    Filed: January 4, 2019
    Date of Patent: May 18, 2021
    Assignee: VIA TECHNOLOGIES, INC.
    Inventors: Nan Hui Li, Neng-An Kuo
  • Patent number: 10977947
    Abstract: A method for vehicle blind zone detection, applied to an electronic device coupled to one or more cameras arranged on a vehicle, the method comprising: setting a capture zone in a current frame image captured by the camera and detecting an object entering the capture zone in the current frame image, wherein the object meeting a capture criterion and a location information of the object meeting the capture criterion are added into a tracking list; performing tracking operations on an existing object, which has been detected and thus added to the tracking list, in one or more previous frame images preceding the current frame image captured by the camera, to obtain a new location information of the existing object in the current frame image, and determining whether to have the existing object remained in the tracking list in accordance with the new location information of the existing object and the detection scope; and making a warning determination in accordance with the location information in the current fra
    Type: Grant
    Filed: February 18, 2019
    Date of Patent: April 13, 2021
    Assignee: VIA TECHNOLOGIES, INC.
    Inventor: Juan He
  • Patent number: 10967852
    Abstract: A method, an apparatus and a system for displaying an image of a vehicle blind spot are provided. The apparatus is coupled to at least one external camera disposed outside the vehicle, at least one internal camera disposed inside the vehicle with a lens facing towards a driver, and at least one display disposed inside the vehicle. The method comprises capturing an image of the external environment of the vehicle by the external camera as an external image, capturing an image including the driver by the internal camera as an internal image, recognizing a face of the driver and a displacement of the face in the internal image, and adjusting a position of an ROI in the external image according to the recognized displacement, to display an image of the ROI on the display corresponding to the external camera. The displayed image of the external of the vehicle may be adjusted according to the posture or the angle of view of the driver, to have the image of the current blind spot by the driver shown correctly.
    Type: Grant
    Filed: March 30, 2020
    Date of Patent: April 6, 2021
    Assignee: VIA TECHNOLOGIES, INC.
    Inventors: Hsueh-hsin Han, Hsuan-chieh Huang
  • Patent number: 10909056
    Abstract: An architecture of a multi-core electronic system is provided. The architecture includes a plurality of first computing cores, a first ring bus, a direct memory access (DMA) engine, and a DMA ring controller. The first computing cores are connected to the first ring bus. The DMA ring controller connects the DMA engine to the first ring bus. The first computing cores communicate with the DMA engine through the first ring bus and make the DMA engine perform a memory operation.
    Type: Grant
    Filed: December 22, 2018
    Date of Patent: February 2, 2021
    Assignee: VIA Technologies, Inc.
    Inventor: Wen-Pin Chiang
  • Publication number: 20200364110
    Abstract: A non-volatile memory apparatus includes an error checking and correcting (ECC) decoding circuit, a first cyclic redundancy check (CRC) circuit, a second CRC circuit, and an interface circuit. The ECC decoding circuit decodes an original codeword to obtain a decoded codeword. The interface circuit receives and provides a first data portion of the decoded codeword to a host. The first CRC circuit performs a first CRC on the first data portion and generates a check status message based on a relationship between a result of the first CRC and a first CRC code of the decoded codeword. The second CRC circuit performs a second CRC on the first data portion to generate a second CRC code. The second CRC circuit determines whether to further change the second CRC code to make the second CRC code not match the first data portion according to the check status message.
    Type: Application
    Filed: August 5, 2020
    Publication date: November 19, 2020
    Applicant: VIA Technologies, Inc.
    Inventors: Yi-Lin Lai, Chen-Te Chen, Ying-Che Chung
  • Patent number: 10824554
    Abstract: A non-volatile memory (NVM) apparatus and an iteration sorting method thereof are provided. The NVM apparatus performs the iteration sorting method to select one target block from a plurality of blocks of a NVM, and to perform a management operation on the target block. The iteration sorting method includes: selecting a plurality of candidate blocks among the blocks of the NVM to join into a sorting set, sorting all of the candidate blocks in the sorting set according to metadata, picking one candidate block with maximum (or minimum) metadata from the sorting set to serve as the target block, and keeping M candidate blocks in the sorting set and discarding the rest of the candidate blocks from the sorting set.
    Type: Grant
    Filed: December 14, 2016
    Date of Patent: November 3, 2020
    Assignee: VIA Technologies, Inc.
    Inventors: Ying Yu Tai, Jiangli Zhu
  • Patent number: 10783032
    Abstract: A non-volatile memory apparatus includes an error checking and correcting (ECC) decoding circuit, a main buffer circuit, a multiplexer, and an interface circuit. The ECC decoding circuit decodes an original codeword to obtain a decoded codeword. The main buffer circuit is coupled to the ECC decoding circuit for receiving and storing a first data portion of the decoded codeword. The multiplexer's first input end is coupled to the output end of the main buffer circuit. The second input end of the multiplexer is coupled to the output end of the ECC decoding circuit. The interface circuit is coupled to the output end of the multiplexer and receives the first data portion from the multiplexer to provide the first data portion to a host.
    Type: Grant
    Filed: July 27, 2017
    Date of Patent: September 22, 2020
    Assignee: VIA Technologies, Inc.
    Inventors: Yi-Lin Lai, Chen-Te Chen, Ying-Che Chung
  • Patent number: 10733107
    Abstract: A non-volatile memory (NVM) apparatus and an address classification method thereof are provided. The NVM apparatus includes a NVM and a controller. The controller accesses the NVM in accordance with a write command of a host. The controller may perform the address classification method. The address classification method includes: providing a data look-up table, wherein the data look-up table includes a plurality of data entries, each of the data entries includes a logical address information, a counter value and a timer value; searching the data look-up table based on the logical address of the write command in order to obtain a corresponding counter value and a corresponding timer value; and determining whether the logical address of the write command is a hot data address based on the corresponding counter value and the corresponding timer value.
    Type: Grant
    Filed: October 7, 2016
    Date of Patent: August 4, 2020
    Assignee: VIA Technologies, Inc.
    Inventors: Ying-Yu Tai, Jiangli Zhu, Jiin Lai
  • Patent number: 10701061
    Abstract: The invention introduces a method for blocking unauthorized applications, at least containing: receiving an input parameter from an application; determining whether the application is authenticated by inspecting content of the input parameter; randomly generating a session key, storing the session key in a file and storing the file in a path that can be accessed by a motherboard support service and the application only when the application is authenticated; and replying with the path and a filename of the file to the application.
    Type: Grant
    Filed: September 18, 2017
    Date of Patent: June 30, 2020
    Assignee: VIA TECHNOLOGIES, INC.
    Inventors: Guanghui Wu, Jinglin Liu
  • Patent number: 10657076
    Abstract: An electronic apparatus and a method of extending peripheral devices are provided. The electronic apparatus includes: a controller; and a plurality of peripheral devices electrically connected to the controller, wherein the plurality of peripheral devices include a plurality of video graphics array display cards, wherein in an initialization phase of the electronic apparatus, the controller allocates input/output resources to a first portion of the video graphics array display cards and does not allocate the input/output resources to a second portion of the video graphics array display cards, wherein the first portion of the video graphics array display cards allocated with the input/output resources is used to display an image in the initialization phase.
    Type: Grant
    Filed: April 3, 2019
    Date of Patent: May 19, 2020
    Assignee: VIA Technologies, Inc.
    Inventors: Kuan-Jui Ho, Yi-Hsiang Wang
  • Patent number: 10649513
    Abstract: An energy regulation circuit including a first voltage regulator, a processor, a second voltage regulator, and a controller is provided. The first voltage regulator adjusts an input voltage to generate an adjustment voltage. The processor increases the adjustment voltage according to the input voltage to generate a boost voltage. An energy accumulator is charged according to the boost voltage. The second voltage regulator adjusts the boost voltage to generate an operation voltage. The controller operates according to the operation voltage.
    Type: Grant
    Filed: July 12, 2017
    Date of Patent: May 12, 2020
    Assignee: VIA TECHNOLOGIES, INC.
    Inventor: Tze-Shiang Wang
  • Patent number: D885369
    Type: Grant
    Filed: August 27, 2018
    Date of Patent: May 26, 2020
    Assignee: VIA Technologies, Inc.
    Inventor: Wen-Chi Chen
  • Patent number: D917324
    Type: Grant
    Filed: March 16, 2018
    Date of Patent: April 27, 2021
    Assignee: VIA TECHNOLOGIES, INC.
    Inventor: Chih-Wei Huang