Abstract: There is provided an automatic correction method for an onboard camera and an onboard camera device. The automatic correction method includes the following steps: obtaining a lane image with the onboard camera and a current extrinsic parameter matrix, and identifying two lane lines in the lane image; converting the lane image into a top-view lane image, and obtaining two projected lane lines in the top-view lane image for the two lane lines; calculating a plurality of correction parameter matrices corresponding to the current extrinsic parameter matrix according to the two projected lane lines; and correcting the current extrinsic parameter matrix according to the plurality of correction parameter matrices. This can be applied in situations where the vehicle is stationary or travelling for automatic correction on the extrinsic parameter matrix of the onboard camera.

Abstract: The present disclosure relates to a neural network image identification system and a neural network building system and method used therein. The neural network building method comprises: forming a combination sequence of instruction graphic tags according to a plurality of instruction graphic tags selected by a user and displayed on a screen; combining a plurality of program sets corresponding to the plurality of instruction graphic tags in an order identical to that of contents in the combination sequence of these instruction graphic tags, to generate a neural network program; and checking whether the combination sequence of instruction graphic tags conforms to one or more preset rules before the neural network program is compiled.

Abstract: A computing apparatus includes a first processing circuit and a second processing circuit. The first processing circuit includes a programmable logic circuit. The second processing circuit includes a general purpose processor that is used to execute an application program to download a bitstream to the first processing circuit for programming the programmable logic circuit to implement a direct memory access (DMA) engine and at least one physical engine (PE). The DMA engine is used to access a first memory through a DMA manner. The at least one PE is used to read data to be processed from the first memory through the DMA engine. The first processing circuit and the second processing circuit are disposed in one chip.

Abstract: A package substrate has a substrate surface and a chip region on the substrate surface. The package substrate includes circuit layers, conductive vias, and byte region rows. The circuit layers are sequentially spaced below the substrate surface. Each conductive via is connected to at least two of the circuit layers. The byte region rows are arranged side by side sequentially from an edge of the chip region to a center of the chip region, and each byte region row includes byte regions arranged in a row. Each byte region includes pads located on the circuit layer closest to the substrate surface. The pads of the byte regions of the byte region row closer to the edge of the chip region extend from the chip region to an outside of the chip region through traces of the circuit layer closer to the substrate surface.

Abstract: A bridge circuit includes an NVMe device controller, a network subsystem, and a data transfer circuit. The NVMe device controller is arranged to communicate with a host via a PCIe bus. The network subsystem is arranged to communicate with an NVMe-TCP device via a network. The data transfer circuit is coupled between the NVMe device controller and the network subsystem, and is arranged to deal with data transfer associated with the NVMe-TCP device without intervention of the host.

Abstract: A computer system includes a processor and a processing circuit. The processor has an embedded memory. The processing circuit is arranged to perform a write operation for writing a first write data into the embedded memory included in the processor. The processor is arranged to load and execute a program code to perform a read operation for reading the first write data from the embedded memory included in the processor.

Abstract: An encoding method for a key Trie includes generating a plurality of meta data by applying encoding to a portion of non-leaf nodes of the key Trie, and storing an encoding result of the key Trie into a storage device, wherein the encoding result includes the plurality of meta data corresponding to the portion of non-leaf nodes, respectively.

Abstract: A non-volatile memory apparatus includes an error checking and correcting (ECC) decoding circuit, a first cyclic redundancy check (CRC) circuit, a second CRC circuit, and an interface circuit. The ECC decoding circuit decodes an original codeword to obtain a decoded codeword. The interface circuit receives and provides a first data portion of the decoded codeword to a host. The first CRC circuit performs a first CRC on the first data portion and generates a check status message based on a relationship between a result of the first CRC and a first CRC code of the decoded codeword. The second CRC circuit performs a second CRC on the first data portion to generate a second CRC code. The second CRC circuit determines whether to further change the second CRC code to make the second CRC code not match the first data portion according to the check status message.

Abstract: A storage device includes a flash memory array and a controller. The flash memory array includes a plurality of blocks. A minimal erase number of blocks have a minimal erase count in the plurality of blocks. When one of the minimal erase number of blocks is erased, the controller subtracts 1 from the minimal erase number.

Abstract: A method for facial image recognition is provided. A plurality of original facial images are received. A plurality of standard facial images corresponding to the original facial images are generated through a standard face generation model. A recognition model is trained by using the original facial images and the standard facial images. The recognition model is tested by using the original facial image test set and a standard facial image test set until the recognition model recognizes that the first accuracy rate of the original facial image test set is higher than a first threshold value and the second accuracy rate of the standard facial image test set is higher than a second threshold value. The original facial image test set is composed of the original facial images obtained by sampling, and the standard facial image test set is composed of the standard facial images obtained by sampling.

Abstract: An authorization method and an authorization system are provided. The authorization method includes displaying, by a service device, authorization information on an e-paper arranged on the service device; obtaining, by a user device, the authorization information from the e-paper; and using, by the user device, the authorization information displayed on the e-paper to perform an authorization operation between the user device and the service device.

Abstract: A data storage system and a global deduplication method thereof are provided. The data storage system includes multiple storage devices and one dispatch device. The dispatch device divides an original data corresponding to a data writing request into at least one data chunk. The dispatch device performs a summary calculation on one data chunk, so as to generate a representative value. The dispatch device performs a first distribution calculation on the representative value, so as to determine a destination location corresponding to the representative value. The dispatch device transmits the data chunk and the representative value to at least one destination storage device among the storage devices through a communication network according to the destination location. The at least one destination storage device checks the representative value, so as to determine whether to store the data chunk in a storage space of the at least one destination storage device.

Abstract: A non-volatile memory (NVM) apparatus and a garbage collection method thereof are provided. The NVM apparatus includes a NVM and a controller. The controller is coupled to the NVM. The controller accesses the NVM according to a logical address of a write command of a host. The controller performs the garbage collection method to release space occupied by invalid data. The garbage collection method includes: grouping a plurality of blocks of the NVM into a plurality of tiers according to hotness of data, moving valid data in one closed source block of a hotter tier among the tiers to one open target block of a cooler tier among the tiers, and erasing the closed source block of the hotter tier to release space.

Abstract: A method for displaying landmark data from a search of a place name keyword, the method includes: inputting the place name keyword to a server to search for a plurality of landmark data, wherein each of the landmark data comprises fields of a landmark name, an objective level category, an address, and an address quoting frequency; sorting the landmark data by an electronic device to a display order, based on a characterized parameter for each of the landmark, wherein the characterized parameter is calculated based on at least a publicity, wherein the publicity is a calculation of the objective level category and the address quoting frequency with respectively weighting to the objective level category and the address quoting frequency; and displaying the landmark data by the electronic device according to the display order.

Abstract: A security system and a security method of stored data are provided. In the security system and the security method, a central processing unit performs hashing operation on a seed code to generate a data access code, which is then compared with a password stored in a storage device. If there is no password in the storage device, the data access code is written into the storage device as the password. On the other hand, if the data access code does not match the password, the storage device denies the access request from the central processing unit.

Abstract: A method for vehicle blind zone detection, applied to an electronic device coupled to one or more cameras arranged on a vehicle, the method comprising: setting a capture zone in a current frame image captured by the camera and detecting an object entering the capture zone in the current frame image, wherein the object meeting a capture criterion and a location information of the object meeting the capture criterion are added into a tracking list; performing tracking operations on an existing object, which has been detected and thus added to the tracking list, in one or more previous frame images preceding the current frame image captured by the camera, to obtain a new location information of the existing object in the current frame image, and determining whether to have the existing object remained in the tracking list in accordance with the new location information of the existing object and the detection scope; and making a warning determination in accordance with the location information in the current fra

Abstract: A method, an apparatus and a system for displaying an image of a vehicle blind spot are provided. The apparatus is coupled to at least one external camera disposed outside the vehicle, at least one internal camera disposed inside the vehicle with a lens facing towards a driver, and at least one display disposed inside the vehicle. The method comprises capturing an image of the external environment of the vehicle by the external camera as an external image, capturing an image including the driver by the internal camera as an internal image, recognizing a face of the driver and a displacement of the face in the internal image, and adjusting a position of an ROI in the external image according to the recognized displacement, to display an image of the ROI on the display corresponding to the external camera. The displayed image of the external of the vehicle may be adjusted according to the posture or the angle of view of the driver, to have the image of the current blind spot by the driver shown correctly.

Abstract: An architecture of a multi-core electronic system is provided. The architecture includes a plurality of first computing cores, a first ring bus, a direct memory access (DMA) engine, and a DMA ring controller. The first computing cores are connected to the first ring bus. The DMA ring controller connects the DMA engine to the first ring bus. The first computing cores communicate with the DMA engine through the first ring bus and make the DMA engine perform a memory operation.