Abstract: A microprocessor includes a register that stores a state and a fetch unit that fetches instructions of a program. The program includes a first instruction followed non-immediately by a second instruction. The first instruction instructs the microprocessor to update the state in the register. The second instruction is a conditional branch instruction that specifies a branch condition based on the register state. The fetch unit dispatches the first instruction for execution but refrains from dispatching the second instruction for execution. Execution units receive the first instruction from the fetch unit and responsively update the register state. The fetch unit non-selectively correctly resolves the conditional branch instruction based on the register state when the execution units have updated the register state.

Abstract: A microprocessor having a plurality of call/return stacks (CRS) correctly resolves a call or return instruction rather than issuing the instruction to execution units of the microprocessor to be resolved. The microprocessor fetches a call or return instruction and determines whether the instruction is the first call or return instruction fetched after fetching a conditional branch instruction that has yet to be resolved. The microprocessor copies the contents of a current CRS to another CRS and designates the other CRS as the current CRS, if the state exists. The microprocessor pushes the address of the next sequential instruction following the call instruction onto the current CRS and fetches an instruction at the call instruction target address if the instruction is a call instruction. The microprocessor pops a second return address from the current CRS and fetches an instruction at the second return address, if the instruction is a return instruction.

Abstract: Device and method capable of dynamically displaying digital images by coordinate conversion on a virtual plane are provided. The device includes a display unit, a storage unit, and a processing unit. The display unit includes a screen. The storage unit stores a digital image. The processing unit establishes a virtual plane including a display region corresponding to the screen of the display unit, projects the digital image on the virtual plane to form an image region, and decides a moving trace of the image region on the virtual plane. When the image region and the display region overlap, the processing unit calculates the overlap and displays a corresponding part of the digital image by reading from the storage unit on a corresponding part of the screen.

Abstract: Systems and methods for graphics data management are described. One embodiment includes a graphics processing system comprising a texture management unit configured to organize texture map data according to a slice major format, wherein the texture map data spans at least one mip level. Furthermore, the graphics processing system comprises a texture cache, wherein the texture cache is coupled to the texture management unit and configured to receive the organized texture map data from the texture management unit.

Abstract: A method for performing hash operations including: receiving a hash instruction that is part of an application program, where the hash instruction prescribes one of the hash operations and one of a plurality of hash algorithms; translating the hash instruction into a first plurality of micro instructions and a second plurality of micro instructions; and via a hash unit disposed within execution logic, executing the one of the hash operations. The executing includes first executing the first plurality of micro instructions within the hash unit to produce output data; second executing the second plurality of micro instructions within an x86 integer unit in parallel with the first executing to test a bit in a flags register, to update text pointer registers, and to process interrupts during execution of the hash operation; and storing a corresponding intermediate hash value to memory prior to allowing a pending interrupt to proceed.

Abstract: A method for performing hash operations including: receiving a hash instruction that prescribes one of the hash operations and one of a plurality of hash algorithms; translating the hash instruction into a first plurality of micro instructions and a second plurality of micro instructions; and via a hash unit, executing the one of the hash operations. The executing includes indicating whether the one of the hash operations has been interrupted by an interrupting event; first executing the first plurality of micro instructions within the hash unit to produce output data; second executing the second plurality of micro instructions within an x86 integer unit in parallel with the first executing to test a bit in a flags register, to update text pointer registers, and to process interrupts during execution of the hash operation; and storing a corresponding intermediate hash value to memory prior to allowing a pending interrupt to proceed.

Abstract: A transmitter identification information (TII) signal detection circuit is suitable for an orthogonal frequency division modulation system. A TII signal detection circuit receives a TII signal and conducts a cross-correlation calculation on the TII signal and a phase reference symbol (PRS) so as to obtain a present cross-correlation result, and then, sums the cross-correlation results obtained by conducting cross-correlations on AVE_TF_NUM-1 pieces of TII signals and the PRS and the present cross-correlation result so as to obtain an accumulated cross-correlation result. After that, a plurality of indices corresponding to a plurality of maximal values in the accumulated cross-correlation result is found out according to the accumulated cross-correlation result.

Abstract: A computer system has an adjustable data transmission rate between a CPU and a core logic chip thereof. In the computer system, the CPU has a power state adjustable in response to a power management control signal issued by the core logic chip. For adjusting data transmission rate between the CPU and the core logic chip, a change of an asserted time of the power management control signal from a first time period to a second time period is first determined to obtain an index value. The data transmission rate is increased or decreased according to the index value.

Abstract: An image morphing method is suitable for generating an intermediate image sequence. First, a control point CP={(pi,qi)}i=1 . . . N is specified and marked in a source image Is({right arrow over (x)}) and a destination image Id({right arrow over (x)}?). Next, an edge gradient parameter (Ise({right arrow over (x)}), Ide({right arrow over (x)}?) is computed according to the source image Is({right arrow over (x)}) and the destination image Id({right arrow over (x)}?). Next, a total objective function E(Df,Db) is computed according to the above-mentioned control point CP and edge gradient parameter (Ise({right arrow over (x)}), Ide({right arrow over (x)}?)). The above-mentioned intermediate image sequence is generated by using the total objective function E(Df,Db). The present invention utilizes the edge gradients of the source image Is({right arrow over (x)}) and the destination image Id({right arrow over (x)}?) to enhance the constraint of image morphing. Thus, the image morphing effect is promoted.

Abstract: Systems and methods for packet forward control. The system comprises a plurality of ports and a processing module configured to receive a packet. The processing module comprises a resource management module and a forward control module. The resource management module detects whether congestion occurs on at least one specific port among the ports. The forward control module determines whether the specific port comprises a predetermined port within the ports, and if so, forwards the packet to at least one of the ports excepting the predetermined port.

Abstract: A operator is located between two converters that convert data between floating-point format and a predetermined format. The operator operates on predetermined format data, which consists of the same sign bit, the same exponent, and the two's complement of the mantissa of the corresponding floating-point data. When the operator is an arithmetic logic unit (ALU), the number of operations for a given calculation can be reduced.

Abstract: Virtual disks management methods and systems. First, a file space is set and a first password is set. A first device code is acquired. The file space is encrypted according to the first password and the first device code to obtain an encrypted file. Thereafter, a designation of the encrypted file is received. A second password is received, and a second device code is acquired. It is determined whether the second password conforms to the first password, and whether the second device code conforms to the first device code. If so, the encrypted file is mounted as a virtual disk.

Abstract: For generating a simulation case to verify an operation of an IC device, a database including a plurality of device description files, a plurality of pattern files and a plurality of command files is established. Files stored in the database and corresponding to an IC device are collected. The collected files are parsed to find out entries to be edited. Specified entries are edited by a user according to the operation of the IC device. A simulation case or a plurality of simulation cases are generated according to the entries.

Abstract: A chipset is electrically connected with an external graphic module, which generates a first graphic signal and outputs it to the chipset. The chipset includes an internal graphic module and a control module. The internal graphic module generates a second graphic signal, and the control module receives the first graphic signal and the second graphic signal. The control module divides the first graphic signal into at least two first graphic sub-signals and divides the second graphic signal into at least two second graphic sub-signals, respectively. When under a first output mode, the control module simultaneously outputs one of the first graphic sub-signals and one of the second graphic sub-signals.

Abstract: A Global Position System signal acquiring system and method is provided in this invention. Pluralities of counters are set, each corresponding to a code bin and a frequency bin of the signal. Subsequently, the signal corresponding to the counters is repeatedly received in a unit of time and the counters are accordingly updated for a pre-determined iteration. At last, a maximum value among the counters is found to acquire the signal corresponding to the counter having the maximum value.

Abstract: A process for fabricating a circuit substrate is provided. A patterned conductive layer having an inner pad is provided on a base layer, a dielectric layer is disposed on the base layer and covers the patterned conductive layer, and a covering layer is disposed on the dielectric layer. A part of the covering layer is removed by dry etching to form a first opening. A part of the dielectric layer exposed by the first opening is removed to form a dielectric opening exposing a part of the inner pad. A patterned mask having a second opening to expose a part of the inner pad is formed on the covering layer. A conductive structure including a conductive block filling the dielectric opening, an outer pad filling the first opening and a surplus layer filling the second opening is formed. Finally, the patterned mask, surplus layer and covering layer are removed.

Abstract: The present invention is directed to a correlation interval synchronization apparatus and method. Correlation is firstly performed on received data, followed by searching peaks in accordance with the output of the correlation. Subsequently, peak intervals are acquired according to the peaks, and the peak interval where the synchronization head position resides is determined. Finally, the synchronization head position is identified within the associated peak interval.

Abstract: A clockless return to state domino logic gate is disclosed responsive to multiple return to state input nodes. A domino circuit has a preset state in which it presets a preset node to a second state. The domino circuit switches to a latch state and switches an output node when the preset node is pulled to a first state. The domino circuit resets back to the preset state and switches the output node back to its default state when a reset node is pulled to the second state. An evaluation circuit pulls the preset node to the second state when the input nodes are in an evaluation state. An enable circuit enables a reset condition when the domino circuit is in its latch state. A reset circuit pulls the reset node to the first state after an evaluation event when the input nodes are no longer in the evaluation state.

Abstract: A clockless return to state domino logic gate including a domino circuit and an input circuit. The domino circuit asserts s preset node and an enable node to a first logic state and asserts an output node and a reset node to a second logic state in a preset state, and switches to a latch state when the preset node is pulled to the second state. In the latch state, the domino circuit pulls the output node to the first logic state and pulls the enable node to the second logic state. The domino circuit resets back to the preset state when the first reset node is pulled to the first logic state. The input circuit controls the domino circuit based on collective state of input signals, and is configured to perform a selected logic function using at least one return to state signal without use of a clock signal.

Abstract: A microprocessor processes a macroinstruction that instructs the microprocessor to write an 8-bit result into only a lower 8 bits of an N-bit architected general purpose register. An instruction translator translates the macroinstruction into a merge microinstruction that specifies an N-bit first source register, an 8-bit second source register, and an N-bit destination register to receive an N-bit result. The N-bit first source register and the N-bit destination register are the N-bit architected general purpose register. An execution unit receives the merge microinstruction and responsively generates the N-bit result to be subsequently written to the N-bit architected general purpose register even though the macroinstruction only instructs the microprocessor to write the 8-bit result into the lower 8 bits of the N-bit architected general purpose register.