Abstract: Systems and methods are disclosed for locking code in cache. A processor comprises a cache and a cache controller. The cache is configured to store a temporary copy of code residing in main memory. Also, the cache is divided into a number of cache ways, where each cache way is further divided into a number of cache way portions. The cache controller is configured to utilize a first signal and a second signal. The first signal designates one of the cache ways as a partial cache way and the second signal defines which ones of the cache way portions of the partial cache way are to be locked.

Abstract: Method and related system for detecting advertising sections of video signal. The invention is capable of integrating detecting results based on different detecting rules, which includes detecting discontinuity of frame images in the video signals, detecting occurrences of frames with specific images, detecting occurrences of repeated frames, and detecting audio divisions in the video signal. Detecting results of these detecting rules are integrated by weighting them according to their accuracy, such that occurrence of advertising can be located.

Abstract: Systems for performing rasterization are described. At least one embodiment includes a span generator for performing rasterization. In accordance with such embodiments, the span generator comprises functionals representing a scissoring box, loaders configured to convert the functionals from a general form to a special case form, edge generators configured to read the special case form of the scissoring box, whereby the special case form simplifies calculations by the edge generators. The span generator further comprises sorters configured to compute the intersection of half-planes, wherein edges of the intersection are generated by the edge generators and a span buffer configured to temporarily store spans before tiling.

Abstract: A memory device and a method thereof. The memory described includes a control module and a single-port memory array. The control circuit generates control signals according to a clock signal, a read command signal and a write command signal. The single-port memory array is accessed according to the control signals.

Abstract: The invention provides a method for controlling the signal gain of a MultiBand Orthogonal Frequency Division Multiplexing (MB-OFDM) baseband receiver. The symbol boundary of a signal is first detected. Power of the signal is then measured according to the symbol boundary, so that a zero-padding section of the signal is not measured. A gain magnitude for amplifying the signal is then determined according to the power of the signal. The signal is then amplified according to the gain magnitude.

Abstract: A structure of a circuit board for improving the performance of routing traces is described as eliminating the resonant effects from the inner layers in a circuit board. For eliminating the stray capacitor effect between the planes in the circuit board, the present invention uses a method for etching an area of a power plane and the area is corresponding to a routing plane. Consequently, the routing trace can make good electric potential reference of a ground plane. Due to the reduction of the stray capacitor, the structure for improving the performance of routing traces of the invention can avoid the resonance effect and parasitic resonance in the circuit board as produced in a high-frequency situation in order to promote the quality of the circuit board.

Abstract: Chipsets capable of preventing malfunction caused by feedback clock distortion are provided, in which a phase frequency detector generates a control voltage according to a first reference clock and a first feedback clock, a voltage-controlled oscillator generates an output clock according to the control voltage, a frequency divider performs a frequency-division on a second feedback clock to obtain the first feedback clock, and a frequency filter estimates swings and frequency of a third feedback clock from an external unit and selectively outputs one of the third feedback clock or the output clock to serve as the second clock.

Abstract: A bus inversion apparatus includes exclusive-OR gates and an inversion detector. The exclusive-OR gates are coupled to an instant data bus and a last data bus. The data buses have a corresponding plurality of bits, where the exclusive-OR gates perform a bitwise comparison of the data buses, and provide an exclusive-OR bus. The states of the exclusive-OR bus indicate whether corresponding bits of the data buses are different. The inversion detector counts the number of the corresponding bits that are different, and indicates that the instant data bus should be inverted. The inversion detector has a plurality of left shift circuits, each configured to perform a logical left shift of input bits as directed by the states of shift bits, where outputs of the each of the plurality of left shift circuits indicate a number of a subgroup of the corresponding bits that are different.

Abstract: A power control device of multi base powers is provided for an optical read/write module of an optical disk drive. The optical read/write module generates a power feedback signal and a temperature signal. The power control device includes a base power selecting module, a current compensating module, a current computing module and a current integrating module. The base power selecting module selects one of a first base power signal and a second base power signal to output a base power signal. The current compensating module generates an operating current compensating signal and a threshold compensating signal according to the power feedback signal, the temperature signal, the base power signal and a function relationship between the temperature signal and the threshold current of the optical read/write module.

Abstract: An inductor structure including a coil layer and at least a gain lead is disclosed. The coil layer is disposed over a substrate and has a plurality of coil turns, wherein one of the coil turns is grounded. The gain lead is disposed under at least one of the inner side and the outer side of the grounded coil turn and is electrically connected in parallel to the grounded coil turn. The width of the gain lead is less than the width of the grounded coil turn.

Abstract: Media drive control system and method. The media drive control system comprises a player console, a user operation filter, and a plurality of playback management devices. The player console provides an instant user operation (UOP) according to a received user command. The user operation filter comprises a queue and a management device. The queue receives and stores a plurality of UOPs, and outputs stored UOPs as control instructions on a first-in-first-out basis. The management device determines whether the queue is full. If the queue is full, the management device discards at least one of the stored UOPs prior to storing the instant UOP in the queue. Each playback management device receives control instructions for controlling corresponding playback devices.

Abstract: A microprocessor includes re-writeable non-volatile state (RNS) addressable by an instruction executed by the microprocessor that instructs the microprocessor to write a new value to the RNS. A plurality of fuses are each readable to determine whether the fuse is blown or unblown, in response to the microprocessor decoding the instruction. A Boolean logic unit performs Boolean operations on the values read from the plurality of fuses to determine a current RNS value. A fuse blowing device blows at least one unblown fuse to change the current RNS value to the new value when the new value is different than the current value. The microprocessor can read the plurality of fuses, perform the Boolean operations, and blow at least one unblown fuse to change the current value of the RNS to a new value multiple times in response to a program running on the microprocessor executing the instruction multiple times.

Abstract: A technique is provided for performing modular multiplication. In one embodiment, an apparatus in a microprocessor is provided for accomplishing modular multiplication operations. The apparatus includes translation logic and execution logic. The translation logic receives an atomic Montgomery multiplication instruction from a source therefrom, where the atomic Montgomery multiplication instruction prescribes generation of a Montgomery product. The translation logic translates the atomic Montgomery multiplication instruction into a sequence of micro instructions specifying sub-operations required to accomplish generation of the Montgomery product. The execution logic is operatively coupled to the translation logic. The execution logic receives the sequence of micro instructions, and performs the sub-operations to generate the Montgomery product.

Abstract: A write adjustment method adjusts recording power, recording time, and recording position of a recorder. The recorder includes a light detecting chip to receive a reflected light signal and generate a recording detection signal to a high pass filter. The high pass filter receives the recording detection signal and outputs a filtering signal. The write adjustment method includes writing first short period data to a disk, acquiring a reference voltage of the high pass filter according to a maximum value and a minimum value of the filtering signal, writing first mixing period data to the disk according to a plurality of predetermined recording times, acquiring a first maximum value and a first minimum value according to the filtering signal and adjusting and determining a first recording power of the recorder when a target value is achieved according to the first maximum value, the first minimum value and the reference voltage of the high pass filter.

Abstract: A method for adjusting clock frequency is disclosed. The method includes halting a central processing unit (CPU) while tuning a clock frequency, thereby enabling multiple clock signals with the tuned clock frequency to be generated.

Abstract: A dynamically scheduled parallel graphics processor comprises a spreader that creates graphic objects for processing and assigns and distributes the created objects for processing to one or more execution blocks. Each execution block is coupled to the spreader and receives an assignment for processing a graphics object. The execution block pushes the object through each processing stage by scheduling the processing of the graphics object and executing instruction operations on the graphics object. The dynamically scheduled parallel graphics processor includes one or more fixed function units coupled to the spreader that are configured to execute one or more predetermined operations on a graphics object. An input/output unit is coupled to the spreader, the one or more fixed function units, and the plurality of execution blocks and is configured to provide access to memory external to the dynamically scheduled parallel graphics processor.

Abstract: A system and method to manage data processing stages of a logical graphics pipeline comprises a number of execution blocks coupled together and to a global spreader that assigns graphics data entities for execution to the execution blocks. Each execution block has an entity descriptor table containing information about an assigned graphics data entity corresponding to allocation of the entity and a current processing stage associated with the entity. Each execution block includes a stage parser configured to establish pointers for the assigned graphics data entity to be processed on a next processing stage. A numerical processing unit is included and configured to execute floating point and integer instructions in association with the assigned graphics data entity. The execution blocks include a data move unit for data loads and moves within the execution block, with the global spreader, and with other execution blocks of the plurality of execution blocks.

Abstract: A method and device of receiving WLAN data. The device comprises a transceiver module and a controller module. The transceiver module transmits first data and receives second data. The controller module is coupled to the transceiver module, and disables the transceiver module for a first period based on interframe space (IFS), upon completion of data transmission in the transceiver module.

Abstract: A method for processing packets of a VLAN in a network switch is provided. The VLAN comprises a plurality of physical LANs and are divided into a plurality of subnets. The method comprises the steps of: receiving a packet through an ingress port of the network switch, wherein the packet is tagged with a VID of the VLAN; finding a VLAN member according to the VID, wherein the VLAN member represents all ports of the network switch dedicated to serving packets of the VLAN; finding a forwarding scope according to the ingress port, wherein the ingress port is one of the ports dedicated to serving packets of a first subnet of the VLAN and the forwarding scope represents all ports of the network switch dedicated to serving packets of the first subnet; and determining an egress port of the packet according to both the VLAN member and the forwarding scope.

Abstract: The through holes in an array manner in the signal layer within the chip-interposed region on a substrate of a BGA package comprise a ball pads array having a plurality of ball pads and a vias array. The vias array has a plurality of vias located interlaces with the ball pads array. The outermost portions of the chip-interposed region are designed in such a manner to have at least two rings of vias for signal transmission and power connection. The interval between every two adjacent vias in the ring is not less than twice of the distance of two ball pads. Upon such an arrangement, the BGA package can have a plurality of dissipation channels that can increase dissipation space, dissipate quickly the heat generated from the IC, and transmit well for signal and power.