Abstract: A method and an apparatus of memory access request priority queue arbitration comprises sorting the requests into plurality of different priority levels firstly. The priority queues of different priority levels are arranged respectively according to the following steps: counting the cycles and latencies of each access request; counting the total cycles; comparing the latencies of each access request and total cycles respectively, if the total cycles is larger than the latency of a request, then arranging one more the same request in the priority queue, else executing the priority queue in order.

Abstract: A circuit and method for timing recovery. The circuit for timing recovery comprises an converter, a timing recovery controller, and a initial phase generator. The converter converts an input signal to sample data with a sampling signal. The timing recovery controller is coupled to the converter, and determines the sampling signal. And the initial phase generator is coupled to the AD converter, detects a change with the sample data only, produces an initial phase based on the change, and controls the sampling signal.

Abstract: A decoding method for MP3 bit streams, which replaces a buffer required in the decoding process by manipulating the order of data decoding. The decoding method includes reading the head and side information of the current frame, and calculating a main data's start address of the current frame. While decoding the main data, the head and side information of subsequent frames are skipped if the reading of the main data is not yet completed. The start address of the next frame is calculated and directly accessed after finished reading the main data of the current frame. An optimum method for accessing frequency lines utilizes the characteristics of the MP3 frequency line, instead of inserting a plurality of zeros in the rzero zone containing successive zeros, the initial boundary address of the rzero zone is memorized.

Abstract: A method for dynamically increasing the data processing capability of a computer system is provided. The computer system comprises a processor, a memory and a chipset. The data processing capability of the computer system is classified into a predetermined number of performance enhancing modes. At least one performance enhancing mode transition condition is checked to determine whether to automatically raise the performance enhancing mode of the computer system. The processor is suspended from using the processor bus during the transition of the performance enhancing mode of the computer system. The performance enhancing mode of the computer system is raised by increasing a first working frequency of the processor, a second working frequency of the processor bus and a third working frequency of the memory. The data processing rate of the computer system is further increased when the performance enhancing mode of the computer system is further raised.

Abstract: A transmitter controlling output power to generate a ramp and a method thereof. The transmitter comprises a baseband module, a transmitter module, and a power amplifier. The baseband module receives a power control level, determines a scaling factor according to the power control level, determines a difference between an upper power limit and lower power limit according to a position on the ramp, and calculates a control signal according to the scaling factor, the lower power limit, and the difference. The transmitter module transmits data. The power amplifier coupled to the baseband module and the transmitter module, outputs the data with the output power according the control signal.

Abstract: A method for centralized dynamic link configuration (CDLC), performed by a processor and a chipset is provided. In the method, the processor first notifies the chipset of CDLC enablement. The chipset then issues a command to the processor after receiving notification of CDLC enablement. The processor broadcasts a preparation completion signal after receiving the command. The chipset asserts a signal and activates a timer to start counting after receiving the preparation completion signal. The processor configures devices of the processor, corresponding to a bus, according to one of multiple sets of first link management mode (LMM) configuration parameters in a first LMM register of the processor, indicated by first link management action field (LMAF) code in a first LMAF register of the processor, after detecting that the signal is asserted.

Abstract: The invention provides a method for Serial-Peripheral-Interface (SPI) data transmission. First, data stored in a first buffer of an SPI controller is transmitted to a second buffer of an SPI slave. A clock signal according to which the SPI slave operates is halted after data stored in the first buffer is completely transmitted. The first buffer is then refreshed with data newly received by the SPI controller while the clock signal is halted. The clock signal is then restarted to operate the SPI slave after the first buffer is refreshed. Refreshed data stored in the first buffer is then transmitted to the second buffer while the clock signal is oscillating. Halting of the clock signal, refreshing of the first buffer, restarting of the clock signal, and transmitting of refreshed data are repeated until the second buffer is full. The buffer size of the second buffer greatly exceeds that of the first buffer.

Abstract: The invention provides a method improving flexibility of at least one direct memory access (DMA) channel. The at least one DMA channel is used by a plurality of DMA engines of a first device to direct data transmission between the plurality of DMA engines of the first device and a second device. An explanatory embodiment of the method comprises: allowing any of a plurality of DMA engines to use any of the at least one DMA channels, and enabling some of the plurality of DMA engines to share a target channel if some of the plurality of DMA engines simultaneously compete for the target channel, one of the at least one DMA channel.

Abstract: The invention provides a memory card detection circuit of a computer. The memory card detection circuit comprises a plurality of query pins through which a memory card is coupled to the computer and a plurality of latch circuits respectively coupled to each of the query pins. The latch circuits generates query signals indicating whether ground bounce occurs in the voltage of the query pins due to a voltage difference between two ends of the query pins shortly after the memory card is coupled to the computer through the query pins. The query signals identify the type of the memory card without waiting until ground bounce is resolved.

Abstract: An apparatus, spread spectrum receiver, and method of controlling a circular buffer, comprising a circular buffer and a controller coupled thereto. The circular buffer receives first data at a first data rate and second data at a second data rate. The controller determines a first range in the circular buffer based on the first data rate and a first time difference between the first write and first read speed, accesses the first data in the first range, estimates a second range in the circular buffer based on the second data rate and a second time difference between the first write and first read speed, and accesses the second data in the second range, where the second range is larger than and partially covered by the first range.

Abstract: In an image-frame processing method, the image frame is outputted from and image sensor by an image processor via the buffering of a memory buffer. The method includes the following steps of: defining at least two storage spaces in the memory buffer; dividing the image frame into a plurality of image portions, each of which has a size corresponding to the size of one of said at least two storage spaces; sequentially storing the image portions into the storage spaces in turn; and sequentially processing said image portions stored in the memory buffer. This method is applicable to processing the image frame with the use of a small-sized memory buffer.

Abstract: A microprocessor includes an instruction translator that translates a store macroinstruction into exactly one fused store microinstruction. The store macroinstruction in the microprocessor's macroarchitecture macroinstruction set instructs the microprocessor to store data from a general purpose register of the microprocessor to a memory location. The fused store microinstruction is an instruction in the microprocessor's microarchitecture microinstruction set. A reorder buffer (ROB) receives the fused store microinstruction from the instruction translator into exactly one of its plurality of entries. An instruction dispatcher dispatches for execution a store address microinstruction and a store data microinstruction to different respective execution units of the microprocessor in response to receiving the fused store microinstruction. Neither the store address microinstruction nor the store data microinstruction occupy any of the ROB entries.

Abstract: A method for generating program code used to describe relationships between a plurality of function names and a plurality of control codes of a device. The method comprises receiving the relationships between the plurality of function names and the plurality of control codes, detecting if one of the function names corresponds to more than one control code and if one of the control codes corresponds to a plurality of function names. Program code is generated to describe the relationships if there are no multiple mappings between the control codes and the function names. A warning message is generated if there is function name corresponding to more than one control code or a control code corresponds to more than one function name.

Abstract: A microprocessor REP MOVS macroinstruction specifies the word length of the string in the IA-32 ECX register. The microprocessor includes a memory, configured to store a first and second sequence of microinstructions. The first sequence conditionally transfers control to a microinstruction within the first sequence based on the ECX register. The second sequence does not conditionally transfer control based on the ECX register. The microprocessor includes an instruction translator, coupled to the memory. In response to a macroinstruction that moves an immediate value into the ECX register, the instruction translator sets a flag and saves the immediate value. In response to a macroinstruction that modifies the ECX register in a different manner, the translator clears the flag. In response to a REP MOVS macroinstruction, the instruction translator transfers control to the first sequence if the flag is clear; and transfers control to the second sequence if the flag is set.

Abstract: An apparatus for ensuring data coherency within a cache memory hierarchy of a microprocessor during an eviction of a cache line from a lower-level memory to a higher-level memory in the hierarchy includes an eviction engine and an array of storage elements. The eviction engine is configured to move the cache line from the lower-level memory to the higher-level memory. The array of storage elements are coupled to the eviction engine. Each storage element is configured to store an indication for a corresponding cache line stored in the lower-level memory. The indication indicates whether or not the eviction engine is currently moving the cache line from the lower-level memory to the higher-level memory.

Abstract: A microprocessor having model specific registers (MSRs) includes, for each of the MSRs, an associated default value that indicates whether the MSR is protected or non-protected and an associated fuse that, if blown, toggles the associated default value from protected to non-protected or non-protected to protected. In one embodiment, microcode that does the following in response to the microprocessor encountering an instruction that accesses a specified MSR: determines whether the fuse associated with the specified MSR is blown or unblown, uses the default value associated with the MSR as an indicator of whether the MSR is protected if the associated fuse is unblown; toggles the associated default value to generate the indicator if the associated fuse is blown; protects access to the MSR if the indicator indicates the MSR is protected; and refrains from protecting access to the MSR if the indicator indicates the MSR is non-protected.

Abstract: Power management of a system. A request may be received to enter a first sleep state for a system. One or more processes may be performed to enter the first sleep state in response to the request to enter the first sleep state. A system memory of the system may be stored in a nonvolatile memory (NVM) in response to the request to enter the first sleep state in order to enter a second sleep state. Power may be removed from the system memory after storing the system memory in the NVM in response to the request to enter the first sleep state. After removing power to the system memory, the system may be in the second sleep state.

Abstract: Resuming from a sleep state. A request may received to resume operation of a computer system from a sleep state to an executing state. A restoring process may be initiated to restore the computer system to an executing state. The restoring process may include loading information from a nonvolatile memory medium to a computer system memory medium. A request may be received from a processor of the computer system to access the computer system memory medium. The request may require access to a portion of the computer system memory medium in the executing state, and may be received prior to completion of the restoring process. It may be determined if the portion of the computer system memory medium has been restored. If the portion of the computer system memory medium has not been restored, the portion of the computer system memory medium may be restored from the nonvolatile memory medium ahead of other portions in the restoring process.

Abstract: A method for improving variable length decoding performance is provided. A variable length decoding module decodes a coded data to obtain a decoded data and a subsequent module receives the decoded data to perform further processing. A buffering module is coupled between the variable length decoding module and the subsequent module, and buffers the decoded data decoded by the variable length decoding module. A read part of the buffering module is cleared so that a content of an unused area of the buffering module is a predetermined value when the subsequent module reads the decoded data from the buffering module, wherein the unused area is a part of the buffering module except for the unread decoded data. The variable length decoding module does not write zero values of the decoded data into the buffering module when the variable length decoding module reads a zero output instruction among the coded data.

Abstract: A digital lock detector for a phase-locked loop. The PLL generates a feedback clock according to a reference clock. The digital lock detector includes a match detector and an arbiter. When a first clock transitions, the match detector checks that whether a second clock transitions in a predetermined time window or not. The match detector generates a match signal if the second clock transitions in the predetermined time window. The arbiter counts a number of the successive match signals and generates a lock signal to indicate a lock state when the number exceeds a first predetermined number.