Abstract: Determining and simultaneously using a base station coupled to a mobile device, the base station comprising a detector for receiving a first identification signal corresponding to a first module and a second identification signal corresponding to a second module from the mobile device. A transmitter for sending a plurality of signals to the mobile device, said plurality of signals is configured to set up communication between the mobile device and the base station. A receiver for receiving a plurality of parameters for determining whether the second module is able to attach to the base station; and a processor for connecting the first and second module in the mobile device to the base station simultaneously in response to a plurality of slots by time multiplexing and the plurality of parameters when the second module is acceptable by the base station, wherein said plurality of slots are determined by the base station.

Abstract: A microprocessor for improving out-of-order superscalar execution unit utilization with a relatively small in-order instruction retirement buffer. A plurality of execution units each calculate an instruction result. The instruction is either an excepting type instruction or a non-excepting type instruction. The excepting type instruction is capable of causing the microprocessor to take an exception after being issued to the execution unit, wherein the non-excepting type instruction is incapable of causing the microprocessor to take an exception after being issued. A retire unit makes a determination that an instruction is the oldest instruction in the microprocessor and that the instruction is ready to update the architectural state of the microprocessor with its result.

Abstract: A package substrate for a multi-package module. The package substrate comprises a substrate having a die region and at least one thermal channel region outwardly extending to an edge of the substrate from the die region. An array of bumps is arranged on the substrate except in the die and thermal channel regions, in which the interval between the bumps is narrower than the width of the thermal channel region. An electronic device with a package substrate is also disclosed.

Abstract: A symmetrical inductor. The inductor comprises first, second, third and fourth semi-circular conductive lines disposed in an insulating layer on a substrate, having first and second ends, respectively. The second semi-circular conductive line makes the first semi-circular conductive line symmetric, in which the first ends of the first and second semi-circular conductive lines are electrically connected to each other. The third semi-circular conductive line is parallel to and located outside the first semi-circular conductive line, in which the second ends of the third and second semi-circular conductive lines are electrically connected to each other. The fourth semi-circular conductive line makes the third semi-circular conductive line symmetric, in which the second ends of the fourth and first semi-circular conductive lines are electrically connected to each other.

Abstract: A PCI Express link state management system and method thereof is disclosed. The PCI Express link state management system includes an upstream device, a downstream device and a link. The upstream device outputs a configuration request to the downstream device to change a device power state of the downstream device. At the time, the link is in a first link state. The downstream device outputs a power entering signal to the upstream device and counts a time period. The link enters to a recovery state and further then return to the first link state if the downstream device does not receive a power request acknowledging signal before the time period is expired.

Abstract: A bus receiver receives at least one first signal and a second signal both generated from a chip connected to a parallel bus. The bus receiver includes a receiving module and a deskewing module. The receiving module is electrically connected to the parallel bus and receives the first signal and the second signal transmitted through the parallel bus. The deskewing module is electrically connected to the receiving module and deskews the phase of the first signal and the phase of the second signal. The first signal and the second signal are in the same phase.

Abstract: The invention is directed to an operating method for an image-sensing unit and the image-sensing device using the same. The image-sensing unit comprises a photogate, a photodiode assembled with the photogate, and a first switch. One terminal of the first switch is coupled to a reference voltage, and the other terminal thereof is coupled to the photodiode. The operating method comprises: (a)Applying a first voltage to the photogate, (b)Turning on a first switch, (c)Turning off the first switch at a first time, (d)The photodiode being irradiated by a light, (e)Stopping applying a first voltage value to the photogate at a second time, (f)Applying a second voltage to the photogate at a third time, and (g)Maintaining the turn-off state of the first switch until a fourth time. The operating method for an image-sensing unit enables the image-sensing device using the same to enhance the dynamic range thereof.

Abstract: An apparatus for adaptive de-interlace of a frame comprises a line-segment difference-value calculating module, a motion-vector calculating module, an intra-block calculating module, a trigger-value producing module, and an image processing module. The line-segment difference-value calculating module computes a difference value of a line segment within the frame. The motion-vector calculating module computes a motion vector of a macro block that is located in the frame and comprises the line segment. The intra-block calculating module computes the amount of intra blocks in the frame. The trigger-value producing module determines whether the amount of the intra blocks is larger than a first threshold or not, so as to select an algorithm for generating a trigger value. The image processing module determines whether the trigger value is larger than a second threshold or not and then selects a de-interlace algorithm for de-interlacing the line segment.

Abstract: A bus cycle trapping system includes at least one register, a north bridge, a south bridge and a central processing unit (CPU). The register is configured to store at least one trapping parameter. The north bridge traps a bus cycle matching the at least one trapping parameter while issuing an activating signal. The south bridge sends a system management interrupt message according to the activating signal. The CPU enters a system management mode according to the system management interrupt and executes a system management interrupt routine for doing a debugging test of the bus cycle matching the trapping parameter.

Abstract: Included are systems and methods for Graphics Processing Unit (GPU) synchronization. At least one embodiment of a system includes at least one producer GPU configured to receive data related to at least one context, the at least one producer GPU further configured to process at least a portion of the received data. Some embodiments include at least one consumer GPU configured to received data from the producer GPU, the consumer GPU further configured to stall execution of the received data until a fence value is received.

Abstract: A circuit board includes a pad, a transmitting trace and a plating bar. The plating bar is used for forming an electroplating metallic layer on the pad, the pad and the transmitting trace are used for the signal transmission. Due to the plating bar causes a noise during the signal transmission, a dielectric layer having at least one opening is adjacent to at least one side of the plating bar to reduce the equivalent dielectric permittivity thereof and to maintain signal transmitting quality.

Abstract: A voltage controlled oscillator (VCO) with improved frequency characteristics is provided. The VCO includes a converting circuit supplied between a bias voltage and a ground voltage for converting the control voltage into a control current, a replica bias circuit coupled to the converting circuit for providing a swing voltage, and a ring oscillating circuit coupled to the replica bias circuit having at least two delay units coupled in series for successively delaying an input signal as the oscillating signal after a period of delay time.

Abstract: A memory access circuit is provided. The memory access circuit includes a latch circuit, a feedback reset circuit, and a gate latch circuit. The latch circuit receives a high level input signal and outputs a first signal. The feedback reset circuit generates a second signal and a reset signal according to the first signal. The gate latch circuit generates a pre-charge signal and an enable signal according to the first signal and the second signal. The memory is accessed according to the pre-charging signal and the enable signal.

Abstract: An integrated circuit and a protection circuit capable of protecting electrostatic discharge (ESD) damage. The integrated circuit comprises a first pad, a ground pad, a second pad, a device circuitry, a discharging unit, and a discharging controller. The discharging unit comprises first and second transistors in series. The discharging controller comprises an ESD connection unit, and a voltage clamping unit. The ESD connection unit, coupled to the first pad and the discharging unit, receives an ESD pulse to establish a first control voltage to turn on the first transistor in the ESD event. The voltage clamping unit, coupled to the ESD connection unit and the first, second and ground pads, clamps the ESD pulse to establish a second control voltage to turn on the second transistor in the ESD event, and receives an operation voltage at the first pad to turn off the second transistor in normal operation.

Abstract: A memory address monitoring device for monitoring a memory includes an address determining module and an identification determining module. A first process has a first process identification and issues a request address to access the memory. The memory saves data of a second process between a beginning address and an ending address of the memory. The second process has a second process identification. In this device, the address determining module receives the request address and determines whether the request address is located between the beginning address and the ending address to generate an address determining result. The identification determining module receives the address determining result, the first process identification and the second process identification, and compares the first process identification with the second process identification to generate an identification determining result when the address determining result is true.

Abstract: An inductor structure disposed over a substrate and including a coil layer is provided. The coil layer has a plurality of coil turns electrically connected with each other. An innermost coil turn of the coil layer has a portion with a narrower width in a region with a higher magnetic flux density than that in the other region with lower magnetic flux density.

Abstract: A branch prediction apparatus having two two-way set associative cache memories each indexed by a lower portion of an instruction cache fetch address is disclosed. The index selects a group of four entries, one from each way of each cache. Each entry stores a single target address of a different previously executed branch instruction. For some groups, the four entries cache target addresses for one branch instruction in each of four different cache lines, to obtain four-way group associativity; for other groups, the four entries cache target addresses for one branch instruction in each of two different cache lines and two branch instructions in a third different cache line, to effectively obtain three-way group associativity, depending on the distribution of the branch instructions in the program. The apparatus trades off associativity for number of predictable branches per cache line on an index-by-index basis to efficiently use storage space.

Abstract: A data transmission system for enabling data to be transmitted from one of a host and a storage device to the other includes a bus controller, a command register, a data register, a storage device controller and a hardware accelerator. The bus controller receives a command packet from the host through a bus. The command register and the data register respectively store the command packet and the data received by the bus controller. The storage device controller controls an accessing action of the storage device. The hardware accelerator generates a control command according to the command packet and drives one of the storage device controller and the bus controller to move the data in the data register to the other according to the control command. The hardware accelerator generates a transmission state packet according to a transmission state of the data and outputs the transmission state packet to the host.

Abstract: An input stream of graphics primitives may be converted into to a predetermined output stream of graphics primitives by a processor in a graphics pipeline. The processor recognizes a predetermined sequence pattern in the input stream of graphics primitives to the processor. The processor determines whether the recognized sequence pattern can be converted into the one of the plurality of predetermined output streams of graphics primitives. If so, the processor identifies a number of vertices in the recognized sequence pattern and reorders the vertices into a predetermined output pattern. Thereafter, the processor outputs the predetermined output pattern corresponding to one or more graphics processing components.

Abstract: A microprocessor capable of dynamically reducing its power consumption based on its varying operating temperature includes a temperature sensor that monitors the microprocessor's operating temperature and a control circuit that includes operating point data. The operating point data includes a first voltage at which the microprocessor may reliably operate at a frequency and at a first temperature, and a second voltage at which the microprocessor may reliably operate at the frequency and at a second temperature. The second temperature is less than the first temperature and the second voltage is less than the first voltage. The control circuit causes the microprocessor to operate at the frequency and at the second voltage rather than at the first voltage when the operating temperature drops below the second temperature while operating at the frequency and at the first voltage.