Abstract: A method of commonizing the pattern density of topography for different layers of semiconductor wafers to improve the Chemical Mechanical Polishing process used during wafer processing is disclosed. In order to achieve a predetermined pattern density of topography on the surface of a wafer, dummy raised lines are inserted as necessary into gaps between active conductive traces on a trace layer. In some embodiments, the predetermined pattern density is in the range of approximately 40% to 80%. In some applications, both the active conductive traces and the dummy raised lines are formed from a metallic material that is deposited in one single step with an insulating layer deposited over both the active conductive traces and the dummy raised lines prior to the Chemical Mechanical Polishing process. In other applications, the dummy raised lines are formed from the insulating layer.

Abstract: An apparatus and method for balancing the flow of molten molding compound above and below an integrated circuit assembly during encapsulation of the assembly. An annular shaped layer of material is placed over the bonding fingers of a leadframe such that the annular shaped layer of material peripherally surrounds the centrally located opening in the leadframe. The annular shaped layer of material has sufficient width and thickness to slow the flow of molten molding material over the top surface of the integrated circuit assembly to the same speed as the flow of molten material under the bottom surface of the integrated circuit package assembly. In so doing, the present invention reduces the formation of blowholes or voids in encapsulated integrated circuit packages.

Abstract: The effectiveness of various types of optical proximity correction schemes for avoiding line shortening are easily evaluated by imprinting a test pattern on a semiconductor wafer. The pattern includes an easily measurable standard measurement element not susceptible to line shortening and a test element having a series of parallel lines with narrow widths comparable to the widths of the circuit features that are susceptible to line shortening. The test element also includes the same optical proximity correction scheme whose effectiveness is to be measured. The entire test pattern is photolithographed onto the wafer and the lengths of measurement element and the test element are measured and compared to determine the effectiveness of the correction. Several test patterns, each with a different form of optical proximity correction, can be lithographed onto a single wafer for a comparative review of the different correction schemes both in focus and out of focus both positively and negatively.

Abstract: The present invention comprises a voltage controlled oscillator (VCO) circuit having high power supply noise rejection. The circuit of the present invention includes an amplifier having positive, negative, and output terminals. A VCO input is coupled to the positive terminal for receiving a control voltage. A replica circuit is coupled to the negative terminal. A replica source follower transistor is coupled to the output terminal and is also coupled to the replica circuit. The replica source follower transistor transmits a replica current from a power supply to the replica circuit and is controlled by the amplifier. The present invention also includes a first and second VCO cell. The first VCO cell and the second VCO cell are both coupled to the replica circuit and to each other and the second VCO cell includes a VCO output for transmitting a VCO output signal.

Abstract: The present invention provides methods of determining a smallest dimension of a fabricated device on a semiconductor substrate, methods of determining width of a structure comprising a refractory metal silicide, methods of determining parameters of a semiconductor device comprising a refractory metal silicide, and methods of determining width of an insulative spacer of a semiconductor device.

Abstract: A method in accordance with the present invention for developing an integrated circuit design using a compilation tool includes: (A) developing at least one HDL template by: (a) creating the HDL template; (b) creating a parameter file and a parameter check file for the HDL template; and (c) encrypting the HDL template; (B) developing design specifications for use in creating HDL for synthesis and for use in compiling one or more macro blocks; (C) creating the HDL for synthesis; and (D) creating netlists for at least one macro block instantiated in the HDL template using the design specifications. A development tool of the present invention implements the method on a computer system to form a portion of an integrated circuit fabrication system.

Abstract: A digital standard cell implemented ring oscillator circuit for placement within an integrated circuit device. In one embodiment, the digital standard cell ring oscillator circuit is used in conjunction with a system for generating non-deterministic (e.g., random) output signals which can be used for data encryption. A random number generator circuit is used within the above system and the standard cell ring oscillator of the present invention is used to provide oscillator signals to different frequency legs of the random number generator circuit and can also be used to supply a jitter clock. The timing characteristics (e.g., frequency) of the standard cell ring oscillator vary with its fabrication process, its fabrication environment, and the temperature when used; timing characteristics are therefore unpredictable from "chip" to "chip" and from one point in time to another with respect to the same "chip." This increases the non-deterministic properties of the random number generator.

Abstract: An endian domain conversion circuit for converting data packets transmitted between two bus interfaces. The novel system advantageously eliminates any requirement for a large bit switch within the circuit's write data path. Instead, endian conversion intelligence is placed into the read data path. Double words (dwords) are individually received from an incoming data packet and bytes are parallel stored into the same byte location of several different first-in-first-out (FIFO) memories. In one example, the dwords are 32-bits each and the number FIFO memories used is four. An entire input data packet is received in this manner, incrementing the write address of the FIFO memories for each dword. Depending on the type of endian domain conversion required, if at all, endian conversion control circuitry of the present invention controls the manner in which the four exemplary FIFO memories are read (via a read pointer) and the manner which their data is supplied over the output bus to generate the output data.

Abstract: Disclosed is an apparatus and method for manufacturing antifuse structures on topographically varying silicon substrates. The antifuse structures are intelligently formed over topographically lower silicon substrate regions such that subsequent via hole etching processes do not over-etch underlying antifuse structures. Also discloses an apparatus and method for designing dummy metallization and polysilicon features in close proximity to antifuse structures such that subsequently deposited dielectric materials are induced to form thicker dielectric layers over antifuse structures. Advantageously, subsequent via hole etching does not substantially remove antifuse structure materials with may cause detrimental ionic contamination or antifuse infant mortality. In this manner, standard via hole etching techniques may be implemented for all inter-layer via holes without concern the concern of over-etching sensitive underlying devices.

Abstract: Repair cells for performing metal-only functional repairs in a cell-based circuit layout design are described. The repair cells include a gate array under layer made-up of a group of uncommitted (not interconnected) transistors. A cluster of cells can be placed within the cell-based design in various locations and can be coupled together to form logic function elements. The repair cells can be added to cell-based designs during the metalization processing steps so as to repair/change the cell-based design's function. Furthermore, repair cells can be used as feedthrough cells to facilitate routing in the cell-based circuit layout. In this case, feedthrough cells having gate array underlayers may be arranged in columns or are placed in strategic spots within the layout to facilitate routing.

Abstract: The system of the present invention comprises a system for implementing a real time capability in peripheral devices. The system of the present invention functions with a computer system including a processor, a memory, and a video controller, each coupled to a system bus. A USB (universal serial bus) controller is also coupled to the system bus for interfacing peripheral devices on a USB cable to the computer system. A first and second register are included in the USB controller for storing a controller frame number and a controller frame remaining, and a second and third register are included in the peripheral device for storing a device frame number and a device frame remaining. The peripheral device is coupled to the USB controller via a USB cable. A screen reference register is coupled to receive the controller frame number and the controller frame remaining from the USB controller and is coupled to receive a reference signal from a video controller.

Abstract: An electronic device is delineated comprising, in combination, a Phased Lock Loop (PLL) having a charge pump, and a mixed signal circuit coupled in parallel to the charge pump. The mixed signal circuit includes analog circuitry for adding charge to and removing charge from capacitors in a Low Pass Filer (LPF) of the PLL. The mixed signal circuit also includes digital circuitry for controlling the initiation and termination of both the charging and discharging operations carried on by the analog portion of the mixed signal circuit. Upon a significant change in system frequency, the mixed signal circuit first fully discharges and then rapidly charges the capacitors in the LPF in a manner which results in a significant reduction in PLL locking time.

Abstract: An integrated circuit driver drives a differential signal over a communication cable, such as a twisted-pair cable. The integrated circuit driver includes a differential pre-driver that receives an input signal having an about 50% duty cycle and produces an amplified differential signal that swings between a power rail level and a ground level. A signal conditioner circuit receives the amplified differential signal and outputs a conditioned differential signal. The conditioned differential signal swings between the power rail level and an intermediate power level. The integrated circuit driver further includes an output driver that receives the conditioned differential signal that swings between the power rail level and the intermediate power level. The output driver produces a differential output signal that is communicated to the communication cable. The differential output signal has an about zero signal crossing and maintains the about fifty percent duty cycle.

Abstract: A low power scannable asynchronous counter which is fully testable and which consumes low power in a functional mode consists of counter cells cascaded through NOR gate circuits to which clock signals are applied for each of the stages or cells. Each of the stages or cells comprises a flip-flop and a multiplexer which together operate as a toggle flip-flop only when all of the previous flip-flops are set. The result is that the flip-flop clock is forced high preventing any transition of the flip-flop internal clock tree for all stages or cells where the output is low. Thus, no power consumption of such stages takes place during functional operation. In the scan test mode, the counter operates as a shift register and it is fully testable.

Abstract: An off-hook state of a telephone associated with a computer is used in order to disable the power management unit of the computer to prevent premature power shutdown while the telephone is being used. A power-managed computer system includes a bus system, and a central processing unit coupled to the bus system. The central processing unit has a normal power mode and a power saving mode. A telephony interface coupled to the bus system has a port for coupling to a telephone system network. A power management unit is also coupled to the bus system and is responsive to bus system activity and to indicia of telephony interface activity. The power management unit causes the central processing unit to be in a power saving mode when both bus system activity and telephony interface activity are less than a predetermined level of activity.

Abstract: A sputter deposition system includes a mobile collimator. The collimator can be magnetically moved into and out of a position between a wafer and a target of material to be sputtered onto the wafer. In addition, magnets are used to levitate the collimator so that it can be removed without solid-solid friction, and the contamination it can cause. The magnets used for levitation are part of a control loop that maintains the orientation of the collimator parallel to the wafer. The system allows for a combination of good deposition step coverage and high fabrication throughput while minimizing opportunities for contamination and breakage that can occur when the wafer is transferred between chambers.

Abstract: A method for verifying the accuracy of an average topography height function of a photostepper is provided, which includes the steps of placing a wafer on the photostepper for subjecting at least one layout disposed thereon to the average topography height function of the photostepper, wherein the layout has a known average topography height; operating the average topography height function of the photostepper to obtain a measured average topography height; and comparing the measured topography height to the known average topography height. A method for compensating for an inaccuracy of the average topography height function of the photostepper which includes the same steps for verifying the function, whereby an error results; and adds the step of compensating subsequent measurements of the average topography height function by a correcting factor equal to the magnitude of the error.

Abstract: A method of automatically optimizing a hierarchical netlist of integrated circuit cells comprising at least one upper-level cell containing a multiplicity of subsidiary cells of lower hierachical level includes receiving data defining said netlist and timing constraints for it, and establishing abstract timing models for all the subsidiary cells. Timing constraints are propagated to at least one selected subsidiary cell and this cell is optimized by means of a flat optimizer to produced an optimized version of the selected subsidiary cell. The optimized version of the selected cell is inserted into the netlist. The timing constraints denote arrival times for signals at inputs of a cell and required times for signals at outputs of a cell and each abstract timing model of a cell comprises timing parameters which enable a delay time between a specified input of a cell to a specified output of a cell to be computed.

Abstract: A technique for self-aligned silicidation of semiconductor devices is disclosed. This technique includes the formation of polysilicon device features extending from a semiconductor substrate. A coating is deposited on the features and substrate. Chemical mechanical polishing is performed to remove a portion of the coating to expose a polysilicon surface of the features. A metallic layer is formed to contact the exposed polysilicon surface of each of the features. A silicide layer is formed for each feature from the polysilicon and the metallic layer in contact therewith.

Abstract: A power control system for a microprocessor, having multiple parallel operated execution units, functions to disable some of the execution units to conserve power and/or reduce heat. The execution units are disabled by preventing the application of clock pulses to these execution units. This operation is effected by a power control unit which enables and disables gates coupled between a source of clock signals and the execution units.