Abstract: The present invention provides for a circuit comprising: an input operable to receive a bit pattern; a bit-operator configured to selectively transpose the bit pattern; a shifter configured to shift the bit pattern following the transposition of the bit pattern; and the bit-operator being configured to transpose the bit pattern following the shift of the bit pattern. The present invention additionally provides a barrel shifter and a method for manipulating a bit pattern.

Abstract: A method and structure for providing ESD protection for an integrated circuit having multiple pairs of voltage supply rails, each pair including a VDD rail and a VSS rail. In one aspect, ESD devices are connected between pairs of supply rails and I/O pins of the integrated circuit, and antiparallel diodes are connected between respective VSS rails and a VSS-ESD rail.

Abstract: A method for producing a glue layer for an integrated circuit which uses tungsten plugs in accordance with the present invention includes: (A) providing a substrate which has a surface, a center, an edge, and a direction normal to the surface; and (B) sputter depositing a glue layer over the surface of the substrate such that an edge thickness of the glue layer measured in the direction normal to the surface at the edge of the substrate is at least 105% of a center thickness of the glue layer measured in the direction normal to the surface at the center of the substrate.

Abstract: The invention encompasses methods of forming pairs of transistor gates. In one aspect, the invention includes a method comprising: a) defining a first region and a second region of a substrate; the first region and second region comprising a first substrate surface and a second substrate surface, respectively; b) improving a lifetime of a low voltage tolerant transistor formed proximate the first substrate surface by cleaning the first substrate surface with a first mixture comprising hydrofluoric acid and hydrochloric acid; c) forming a first transistor gate over the first substrate region and incorporating the first transistor gate into the low-voltage tolerant transistor; and d) forming a second transistor gate over the second substrate region and incorporating the second transistor rate into a high-voltage tolerant transistor.

Abstract: The invention relates to integrated circuits and to via hole structures which include a tungsten silicide barrier layer and to methods of forming such via hole structures. In an exemplary embodiment, a metal layer is formed on a sidewall and a bottom surface of the via hole, a WSi.sub.x barrier layer is formed on the first metal layer by chemical vapor deposition and the via hole is subsequently filled with a metal. The tungsten silicide barrier layer effectively suppresses device degradation resulting from the release of gaseous species from the sidewall of the via hole during plug formation. Semiconductor devices can thus be fabricated which are immune or less susceptible to metal open failures due to incomplete via filling.

Abstract: An integrated circuit structure includes a conductive layer, a first dielectric layer overlying the conductive layer, a second dielectric layer overlying both the first dielectric layer and the conductive layer and a planarizing layer overlying the second dielectric layer. The conductive layer has a lateral dimension which is greater than a corresponding lateral dimension of the first dielectric layer. Thus the conductive layer and the first dielectric layer form a stepped, pyramidal shaped island. As a result of the stepped, pyramidal shape, the overlying planarizing layer forms with a more planar upper surface than if the sidewall of the island had a vertical profile. In one preferred embodiment of the present invention, the conductive layer is formed from tungsten-silicide, and both of the dielectric layers are either silicon dioxide or silicon nitride.

Abstract: A method and apparatus for optimizing sample fetching in a peripheral component interconnect (PCI) environment. In one embodiment the present invention generates a sample page base address corresponding to a first part of a first address received from a digital signal processor (DSP). The generated sample page base address is then stored in a sample page base address cache which can be accessed by the DSP without accessing a PCI bus. The first part of the first address is compared to a first part of a second address. Provided that the first part of the first address and the first part of the second address are the same, the present invention combines a second portion of the second address sent from the DSP with the generated sample page base address stored in the sample page base address cache. In so doing, the present invention generates a complete address of a sample to be fetched without accessing the PCI bus.

Abstract: A method and system for measuring the thickness of a patterned film. In one embodiment, a first patterned film is impinged with electromagnetic radiation having a wavelength which varies within a given wavelength range. The electromagnetic radiation reflected from the first patterned film is measured. The thickness of the first patterned film is then measured using thickness measuring equipment. The determined thickness of the first patterned film is then correlated with the measured reflectance of the electromagnetic radiation from the first patterned film. A second patterned film is then impinged with electromagnetic radiation having a wavelength which varies within the given wavelength range. The electromagnetic radiation reflected from the second patterned film is measured. The present invention uses the previously determined correlation to determine the thickness of the second patterned film.

Abstract: Disclosed is an aluminum filled via hole for use in a semiconductor interconnect structure. The aluminum filled via hole of the semiconductor interconnect structure includes a first patterned metallization layer lying over a first dielectric layer. A second dielectric layer overlying the first patterned metallization layer and the first dielectric layer. An aluminum filled via hole defined through the second dielectric layer and in contact with the first patterned metallization layer. The aluminum filled via hole has an electromigration barrier cap over a topmost portion of the aluminum filled via hole that is substantially level with the second dielectric layer. The electromigration barrier cap having a thickness of between about 500 angstroms and about 2,500 angstroms.

Abstract: A method and apparatus for attenuating jitter in digital signals. A recovered clock is derived from the digital signal and the digital signal is stored in a buffer. The derived clock is input to an input counter which counts a predetermined number of degrees out of phase with an output counter. When the input counter is at a maximum counter value, the output counter value is latched to the address inputs of a ROM look-up table, which outputs a coefficient to a numerically controlled oscillator (NCO). The NCO includes a low frequency portion that adds the coefficient successively to itself and outputs a carry out (CO) signal. A high frequency portion of the NCO receives a high frequency clock and preferably divides down the high frequency clock to a clock frequency which is centered at the desired output frequency. The high frequency portion preferably includes an edge detect circuit that receives the CO signal and adjusts the frequency of the output clock to produce a compensation clock.

Abstract: A programmable resistor is composed of two layers. A first layer of the programmable resistor has a substantially lower resistance than a second layer of the programmable resistor. The programmable resistor is programmed by placing a signal across the programmable resistor. A resulting current generated by the signal travels in parallel through the first layer of the programmable resistor and the second layer of the programmable resistor. The voltage of the signal is of a sufficient level so that a first portion of the resulting current which travels through the first layer causes a break in the first layer of the programmable resistor. However, the voltage of the signal is not of a sufficient level to allow a second portion of the resulting current which travels through the second layer to cause a break in the second layer of the programmable resistor.

Abstract: A counting system with a dynamic maximum count includes a counter, match logic, and a maximum count controller. The counter has a present count register, a clock (or event indicator) event input, and a reset input. The maximum count controller can be programmed with an adjustable maximum count stored in a maximum count register. The match logic includes a count-wide AND gate fed by NAND gates. Each NAND gate has an inverted input coupled to a respective bit position of the present count register and an uninverted input coupled to a respective bit position of the maximum count register. The function of the match logic is to indicate a match whenever the present count has a 1 at every bit position that the maximum count has a 1, irrespective of the present count values at bit positions at which the maximum count has 0s. Thus, imperfect matches are provided for. The values of the imperfect matches always exceed the values of perfect matches, so they are not usually encountered.

Abstract: A self-aligned contact etch and method for forming a self-aligned contact etch. In one embodiment, the present invention performs an oxide selective etch to form an opening originating at a top surface of a photoresist layer. The opening extends through an underlying oxide layer, and terminates at a top surface of a nitride layer which underlies the oxide layer. Next, the present invention performs a nitride selective etch to extend the opening through the nitride layer to an underlying contact layer. In the present invention, the nitride selective etch causes the photoresist layer to be etched/receded. The nitride selective etch of the present invention further causes the oxide layer to be etched at and near the opening at the interface between the photoresist layer and the oxide layer. As a result, the opening is rounded at the top edge thereof when the layer of photoresist is removed.

Abstract: The differential MOS current-mode logic structure of the present invention is comprised of a differential MOS transistor pair and a complementary MOS (CMOS) transistor for each of the transistors comprising the differential MOS pair. The gates of the CMOS transistors are coupled to the gates of the differential MOS pair. Since the gates of the differential MOS pair receive a differential signal from the inputs, the voltage between the gate and the source, Vgs, for each of the transistors comprising the MOS differential pair is not fixed. As a result, the gain of the CMOS current-mode logic structure of the present invention is high. In addition, since the gates of the CMOS transistors are coupled to the gates of the differential MOS pair, the current for the CMOS transistors is increased when charging the node capacitance and is decreased when discharging the node capacitance.

Abstract: A first synchronization signal is used by a master base station and a remote base station in a digital cordless communication system. The master base station generates a second synchronization signal. The second synchronization signal is used to transfer information over a transmission medium between the master base station and the remote base station. The master base station generates the first synchronization signal from the second synchronization signal. Information is transferred over the transmission medium between the master base station and the remote base station using the second synchronization signal. The remote base station generates the first synchronization signal from the second synchronization signal. The first synchronization signal is utilized by the master base station and the remote base station for digital cordless communication.

Abstract: A voltage controlled oscillator (VCO) circuit having low sensitivity to fabrication process variation, operating temperature variation, and power supply noise. The circuit of the present invention includes a current source controller, a bias circuit, and a first and second VCO cell. The first and second VCO cells are coupled to each other and are coupled to the bias circuit. The VCO circuit of the present invention also includes a VCO output for transmitting a VCO output signal to external electronics. A bias circuit current source is coupled to the bias circuit to transmit a bias circuit current from a power supply to the bias circuit. A first current source is coupled to the first VCO cell to transmit a first current from the power supply to the first VCO cell. A second current source coupled to the second VCO cell to transmit a second current from the power supply to the second VCO cell.

Abstract: Discloses is an apparatus and method for cleaning the edges of semiconductor wafers by using a particle withdrawing means having pre-formed, low-tack adhesive material that removes the particles from the edges of the wafers and retains the particles thus removed.

Abstract: The present invention relates to a system and method for supporting DMA I/O devices. A PCI-PCI bridge is provided to support DMA I/O devices on the PCI bus. Through the use of two signal lines and a serial link, DMA transfers may be accomplished over the PCI bus. A PCI-ISA dock bridge is also provided to allow the system to support DMA I/O devices and ISA masters (i.e., any device including DMA I/O devices on the ISA bus that generates ISA cycles) on the ISA bus.

Abstract: A method for manufacturing probe tips suitable for use in an atomic force microscope (AFM) or scanning tunneling microscope (STM) begins by depositing a layer of a first material over a substrate and then patterning the layer of the first material to define apertures wherever probe tips are to be formed. Next, a layer of a second material is deposited using an unbiased high density plasma chemical vapor deposition (HDPCVD) process to form sharp probe tips in the apertures in the layer of the first material. The HDPCVD process also forms a sacrificial layer of the second material on top of the portions of the first material not removed by the patterning step. The sacrificial layer at least partially overhangs the apertures in the first material, forming a shadow mask during the deposition process which gives rise to a sharp probe profile.

Abstract: A processor is provided for an improved semiconductor etching system which generates a series of multi-bit digital output code words. The processor provides an endpoint detector for determining if one of the digital output code word has reached a predetermined endpoint level and for generating a control signal to stop etching of a wafer. The processor further provides a standard endpoint curve corresponding to standard etching of a standard wafer. A normalizer is provided for normalizing the current endpoint curve generated from the series of multi-bit digital code words for a wafer being etched with respect to the standard endpoint curve and for providing a normalized current endpoint curve.