Abstract: A method for transferring data is performed by a first input/output device in order to perform a data transaction with a host device. The first input/output device receives a first data transaction request from the host device. The first input/output device stops the first data transaction. The first input/output device then requests a data second transaction with a second input/output device and asserts a request signal. The first input output device continuously asserts the request signal even when receiving a stop signal from the second input/output device. The first input/output device retries the second data transaction with the second input/output while continuously asserting the request signal. Upon completing the second data transaction with the second input/output device, the first input/output device releases the request signal. The first input/output device then completes the data transfer with the host device.

Abstract: The present invention includes differential devices and methods of protecting a semiconductor device. One aspect of the present invention provides a differential device adapted to be coupled to a ground connection, the differential device comprising: a first interconnect; a second interconnect; a common diffusion region; a first MOS device coupled with the common diffusion region and the first interconnect; a second MOS device coupled with the common diffusion region and the second interconnect; and a tail MOS device coupled with the common diffusion region and adapted to be coupled to a ground connection.

Abstract: The present invention provides for a hexagonal semiconductor die, semiconductor substrates and methods of forming a semiconductor die. One embodiment of the present invention provides a method of forming a semiconductor die comprising: providing a semiconductor wafer; forming an array of regular hexagonal dies upon the wafer, the array being formed in a two-dimensional honeycomb configuration; forming circuitry upon individual ones of the hexagonal dies; separating the hexagonal dies by laser cutting; and attaching a plurality of electrical contacts to the circuitry of individual ones of the hexagonal dies.

Abstract: A method for preventing oxygen microloading of an SOG layer. In one embodiment of the present invention, hydrogen is introduced into an etching environment. An etching step is then performed within the etching environment. During the etching step an SOG layer overlying a TEOS layer is etched until at least a portion of the underlying TEOS layer is exposed. The etching step continues and etches at least some of the exposed portion of the TEOS layer. During etching, the etched TEOS layer releases oxygen. The hydrogen present in the etching environment scavenges the released oxygen. As a result, the released oxygen does not microload the SOG layer. Thus, the etchback rate of the SOG layer is not significantly affected by the released oxygen, thereby allowing for controlled etchback of the SOG layer.

Abstract: A radio controller arrangement for controlling communication signal timing in a duplex radio-frequency TDMA radio includes a TDMA timer that generates a receive timing signal and a microprocessor circuit. The microprocessor circuit commands the TDMA timer to activate the radio to receive a signal and converts the signal into packets having synchronization and data fields. The TDMA timer synchronizes a beginning of a data collection operation to the synchronization field and locates the beginning of the data field based on the end of the synchronization field. The TDMA timer collects data from the data field until it detects the end of the data field. The TDMA timer then commands deactivation of the radio. The radio controller arrangement may be incorporated into a communication device or used in connection with a method for controlling communication signal timing.

Abstract: A floating-point processor nominally capable of single and double, but not extended, precision execution stores operands in extended-precision format. A format converter converts single and double precision source values to extended-precision format. Trap logic checks the apparent precision of the extended-precision operands and the requested result precision to determine whether the floating-point processor can execute the requested operation and yield the appropriate result. If the maximum of the requested precision and the maximum apparent precision of the operands is single or double, the requested operation is executed in hardware. Otherwise, a trap is issued to call an extended precision floating-point subroutine. This approach augments the class of operations that can be handled in hardware by a double-precision floating-point processor, and thus improves the floating-point computational throughput of an incorporating computer system.

Abstract: A method of making an inter-metal oxide layer over a patterned metallization layer of a substrate, and the resulting structure having the inter-metal oxide layer are provided. The method includes depositing a fluorine doped high density plasma (HDP) oxide layer over the patterned metallization layer. The fluorine doped HDP oxide layer is configured to evenly deposit in high aspect ratio regions of the patterned metallization layer. The method also includes depositing a plasma enhanced chemical vapor deposition (PECVD) oxide layer over the fluorine doped HDP oxide layer. The PECVD oxide layer is doped with a phosphorous material. A CMP operation is then performed over the PECVD oxide layer to remove topographical oxide variations, such that the CMP operation will be configured to preferably leave at least a coating of the PECVD oxide layer over the HDP oxide layer.

Abstract: Disclosed is a redistribution layer having a patterned metallization layer for use in a flip chip integrated circuit device and a method for making the same. The redistribution layer includes a plurality of slot pads arranged along a periphery of the redistribution layer. The plurality of slot pads are formed from the patterned metallization layer. An array of bump pads are arranged in an inner portion of the redistribution layer such that the plurality of slot pads surround the array of bump pads, and the array of bump pads are formed from the patterned metallization layer. The redistribution layer further includes a plurality of traces that are formed from the patterned metallization layer and are configured to interconnect the plurality of slot pads to the array of bump pads. Each of the traces has a width that is selected to substantially equalize a resistance parameter associated with each of the plurality of traces.

Abstract: A complementary conditioning system for use in chemical mechanical polishing (CMP). The present invention functions with a CMP machine adapted for polishing a semiconductor wafer having tungsten components fabricated thereon. A polishing pad is mounted on the CMP machine. The polishing pad has a polishing surface configured for polishing the semiconductor wafer and its tungsten components. The performance of the polishing surface is characterized by a polishing efficiency. A complementary end-effector is mounted on the CMP machine. The complementary end-effector is adapted to chemically complement the tungsten components on the semiconductor wafer. The complementary end-effector is further adapted to contact the polishing surface and improve the polishing efficiency by chemically enhancing the polishing surface, thereby obtaining a more efficient removal rate for the chemical mechanical polishing.

Abstract: The present invention comprises a system for efficiently using non-volatile memory in an embedded system. The system of the present invention includes an embedded system having a processor, a volatile memory, and a non-volatile memory. A decompression algorithm is stored in the non-volatile memory along with a main program. When the embedded system is powered up, the decompression algorithm is executed by the processor. The decompression algorithm operates on compressed software stored in the non-volatile memory. The compressed software includes data needed to initialize the main program. After the operation of the algorithm, the decompressed software is loaded into the volatile memory, thereby initializing the main program. Since the software for initializing the main program is stored in non-volatile memory in a compressed state, and since the decompression algorithm is compact, the present invention efficiently utilizes non-volatile memory space.

Abstract: An integrated circuit includes a memory array implemented with as few as two transistors, and four access lines per cell. The array includes row lines and bit lines, with the internally-arranged bit lines shared by adjacent cells. According to one embodiment, each memory cell is accessed in response to levels established on selected ones of the row and bit lines, and two adjacent memory cells are located on either side of one of the bit lines. This bit line interconnects a first MOS-based transistor in one of the two memory cells and a second MOS-based transistor in the other of the two memory cells. Other aspects of the invention are directed to advantages concerning the laying out of interconnects used in each memory cell. For example, the first MOS-based transistor can have its drain connected to the drain of the second MOS-based transistor using an interconnecting layer arranged substantially at a right angle relative to the first direction or at an acute angle relative to the first direction.

Abstract: A method and apparatus for maintaining coherency in CPU and bus device data transactions in a computer system. A CPU may write data items to a memory shared with bus devices and may also write data items to a write buffer in a bridge circuit which are to be sent out on a device bus, such as a PCI bus. When the CPU writes a data item to the shared memory after writing a data item to the write buffer, a dirty bit is set for each location in the write buffer that stores a data item. When a bus device requests access to the shared memory, the dirty bits are checked. If the dirty bits are set, the bus device is denied access to the shared memory to maintain write coherency. When bus device access is denied, the bus device is informed to retry its request at a later time, and data items in the write buffer are flushed to devices on the bus.

Abstract: Disclosed is a semiconductor chip and method for making a semiconductor chip having strategically placed composite metallization. The semiconductor chip includes a topmost metallization layer that defines a plurality of patterned features including a plurality of input/output metallization pads for receiving an associated plurality of gold bonding wires. An inter-metal oxide layer that is defined under the topmost metallization layer. The semiconductor chip further includes an underlying metallization layer that is defined under the inter-metal oxide layer in order to electrically isolate the topmost metallization layer from the underlying metallization layer. The underlying metallization has a plurality of patterned features, and portions of the plurality of patterned features lie at least partially in locations that are underlying the plurality of input/output metallization pads.

Abstract: Disclosed is a network of on-chip capacitive structures for suppressing power supply inductive noise, methods for making, and systems for designing the on-chip capacitive structures. The network includes a plurality of dummy active regions that are dispersed throughout an integrated circuit design that has a plurality of active regions. The plurality of dummy active regions are separated from the plurality of active regions by at least a bloat distance. The network further includes a network of dummy polysilicon lines that are configured to overlie selected dummy active regions. The network of dummy polysilcon lines that overlie the selected dummy active regions function as dummy gates. In this embodiment, the selected dummy active regions and the dummy polysilicon lines that overlie the selected dummy active regions form the network of on-chip capacitive structures.

Abstract: A virtual contiguous system for combining multiple and arbitrarily-sized and aligned digital data packets from a PCI bus to a DSP circuit is disclosed. Information from the PCI bus is supplied directly to a plurality of FIFO RAM memory units. Each packet of digital data includes data packet descriptors identifying at least the start address for each data packet and the size of each data packet. The system utilizes this information to operate a read pointer and a write pointer to remove data from the FIFO RAM memory units on a sequential bit-by-bit basis and to supply said data packets to said RAM memory units by means of a write pointer operated by said control circuit. The information transfer is managed on the read side of the FIFO RAM memory units with minimal processing on the write side.

Abstract: The present invention comprises a priority arbitration system for interfacing a plurality of PCI agents coupled to a peripheral component interconnect (PCI) bus such that high priority PCI agents are satisfied without starving low priority PCI agents. The system of the present includes a PCI bus adapted to transmit data signals. At least one high priority PCI agent is coupled to the PCI bus. At least one low priority PCI agent is coupled to the PCI bus. An arbiter is coupled to the high priority PCI agent and the low priority PCI agent via the PCI bus. The arbiter grants ownership of the PCI bus to the high priority PCI agent prior to granting ownership to the low priority PCI agent. After being granted ownership, the high priority PCI agent becomes an interim low priority PCI agent. The low priority PCI agent is accorded a higher priority by the arbiter than the interim low priority PCI agent.

Abstract: An anti-fuse structure and method for forming such structure. In one embodiment, the anti-fuse structure of the present invention includes a dielectric layer which is deposited over a metal layer. The semiconductor substrate is then masked and etched so as to form openings in the dielectric layer. Metal is deposited over the semiconductor substrate and is polished so as to remove the metal which overlies the dielectric layer so as to form a plug which extends through the dielectric layer and which electrically connects to the metal layer. An amorphous silicon block is then deposited, masked and etched so as to form an amorphous silicon block over the plug. A metal layer is then deposited, masked and etched so as to form an interconnect. The amorphous silicon block lies between the metal layer and the interconnect so as to prevent the flow of electrical current until such time as the anti-fuse is activated.

Abstract: The present invention provides methods of synchronization, personal handy-phone system stations, and phase lock loops. Synchronization of a personal handy-phone system station with a telecommunication network, and another communication station are provided. One method of synchronization comprises: providing a counter configured to generate a plurality of counter values; storing a first counter value; detecting a reference event; latching a second counter value responsive to the detecting of the reference event; comparing the first counter value and the second counter value to detect phase drift; and compensating for phase drift responsive to the comparing.

Abstract: Within a dual gate oxide process, gate oxide is formed within regions on a substrate. Gate material, such as polysilicon, is placed over a first region. The gate material extends over field oxide surrounding the first region. Gate oxide within a second region is stripped. The gate material over the first region prevents gate oxide within the first region from being stripped. A new layer of gate oxide is formed within the second region. A first transistor gate is formed within the second region. The gate material which is over the first region is etched to form a second transistor gate.

Abstract: Disclosed is a method for automating support pillar design in air dielectric interconnect structures. The method includes selecting features having an interconnect dimension from a first mask. Providing an intermediate support pattern defining a pillar spacing. Identifying overlap regions where the features selected from the first mask overlap the intermediate support pattern. The method further including filtering the overlap regions to eliminate features that are less than the interconnect dimension. The filtering being configured to define discrete pillar locations associated with the first mask.