Abstract: A computer system includes a microprocessor running in big-endian mode and both big-endian and little-endian peripherals, including a little-endian SCSI controller that controls a hard disk. When a program calls for a data transfer between the hard disk and random-access memory, the operating system determines a peripheral-accessible memory address range for the data transfer. A bridge driver intercepts this range and determines whether or not the data needs to be swizzled to take into account differing endianness. The determination is encoded into the most significant bit of a processor-assertable address range, and the bits of lesser significance indicate the peripheral-accessible address range. The processor-assertable address range is conveyed to the SCSI controller originating the data transfer. A communications bridge extracts the processor-assertable address from the origination information from the SCSI controller.

Abstract: A static, in-circuit programmable memory device is provided where the storage element employed is a bi-layer programmable resistor. A specialized programming and readout circuit is provided for each storage element, allowing a known word-line/bit-line memory architecture (commonly used with fuse type memories) to be adapted to a memory element that conducts in both of two different states. The programming and readout circuit may take the form of a merged bipolar/FET device. A bipolar transistor is used for programming and also provides a diode action to prevent sneak path currents from flowing when a storage element is not selected. The bipolar transistor may be a parasitic bipolar transistor. An FET is used for readout. Storage elements are paired, one storage element of each pair functioning as a reference element.

Abstract: A device and method for determining parasitic resistances in a metal oxide silicon field effect transistor (MOSFET). In one embodiment of the present invention, respective total resistances between a plurality of pairs of varyingly spaced apart first contacts of a first test structure are measured. The contact resistance between the plurality of first contacts and a first silicided region and a sheet resistance per unit length of the first silicided region are calculated from the previously measured respective total resistances. Next, respective total resistances between a plurality of pairs of varyingly spaced apart second contacts of a second test structure are measured. The present invention then calculates from the previously measured respective total resistances various resistance components contributing to a total resistance between any pair of the plurality of second contacts.

Abstract: A predictive arbitration system for interfacing a plurality of peripheral component interconnect (PCI) agents coupled to a first PCI bus with a second PCI bus. In one embodiment, the present predictive arbitration system includes a first PCI bus adapted to transmit data signals. A plurality of PCI agents are coupled to the first PCI bus. A predictive arbiter is coupled to both the first PCI bus and a second PCI bus. The predictive arbiter is also coupled to the plurality of PCI agents. The predictive arbiter is configured to receive requests for access to the first or second PCI bus from any of the plurality of PCI agents. The predictive arbiter, upon receiving requests for access, transmits one of the requests to a second arbiter coupled to the second PCI bus, wherein the selected and transmitted request originates from a selected one of the plurality of PCI agents. The predictive arbiter is also adapted to receive a grant signal from the second arbiter in response to the selected and transmitted request.

Abstract: The invention relates to integrated circuits and to methods of forming self-aligned silicidation structures. In an exemplary embodiment, a first insulating layer is formed on the surface of a semiconductor substrate which includes an electrode. A second insulating layer is formed over the first insulating layer and a photoresist pattern is formed over a silicide exclusion area. Exposed portions of the first and second insulating layers are removed by one or more etching steps, wherein an etchant used to remove the exposed portions of the second insulating layer has a higher selectivity for the second insulating layer than for the first insulating layer. A silicide layer can then be formed over the surface of the semiconductor substrate except for silicide exclusion areas. Modification of the profiles of features underlying the first insulating layer, such as sidewall spacer and field oxides can thereby be prevented.

Abstract: A portable computer and corresponding docking station, where the portable computer may be inserted into or removed from the docking station without concern relating to the state of either the portable computer or of the docking station. The hot docking sequence is performed by establishing a direct connection to the primary PCI bus without the risk of any possible system damage, file damage, or data loss. This can be accomplished even while the portable computer system is powered on and is actively running. The present invention prevents glitches from occurring in pre-existing pins and adds four new pins to implement this novel hot docking sequence. Furthermore, hot undocking can be readily performed as well by basically reversing the docking sequence.

Abstract: An improved output driver that minimizes source point reflections when driving a signal on a transmission line by generating a constant source impedance. The improved output driver uses a transistor switching circuit for generating a nearly constant channel impedance when transistor switching circuit is enabled and is not operating in a saturation mode. A switched diode circuit is coupled in parallel to the transistor switching circuit for generating a nearly constant source impedance when a sufficient voltage to bias the switch diode circuit is applied. Control circuitry is coupled to both the transistor switching circuit and to the switched diode circuit for enabling and disabling the transistor switching circuit and the switched diode circuit. By alternatively enabling and disabling the transistor switching circuit and the switched diode circuit the control circuit is able to generate a constant source impedance.

Abstract: Disclosed is a method for making a semiconductor pressure transducer structure in CMOS integrated circuits. The method includes patterning a first metallization layer that lies over an first oxide layer to produce a first patterned metallization layer that is not in electrical contact with a substrate. Forming a tungsten plug in a second oxide layer that overlies the first patterned metallization layer, such that the tungsten plug is in electrical contact with the first patterned metallization layer. Patterning a second metallization layer that overlies the first patterned metallization layer and the tungsten plug to produce a second patterned metallization layer. The patterning of the second metallization layer is configured to prevent the second patterned metallization layer from completely overlying the tungsten plug. The method further includes submerging the pressure transducer structure in a basic solution having a pH level that is greater than about 7.

Abstract: A PCI bus master supporting cascading PCI arbitration. The cascading arbitration allows another PCI initiator on the same bus to share the request and grant signal pair to/from the PCI central arbiter. This allows two PCI devices to appear as a single source to the PCI central arbiter. When a request and grant signal pair are cascaded, they are connected to a subordinate arbiter contained within the cascading bus master. The subordinate arbiter is connected to an internal request and grant signal pair from the cascading bus master, and to an external request and grant signal pair from the cascaded device. The cascading PCI bus master then arbitrates between its internal request and the external cascaded device request and issues the resulting request to the central PCI arbiter. When the grant signal from the central arbiter is returned, the cascading bus master routes it to the appropriate internal or external device. Thereby, bus master support signals can be expanded without having to add a costly bridge.

Abstract: A method of plasma etching photoresist and sidewall polymer with an etch gas mixture comprising a fluorine containing gas (CF.sub.4 or NF.sub.3) and H.sub.2 O demonstrating very aggressive ashrate of photoresist but maintains an exceptionally low etch rate for titanium nitride and other metals is provided. The very low TiN etch rate permits the inventive method to effectively breakdown sidewall polymer without removing any significant amount of these metals. The invention is particularly suited for stripping sidewall polymer from etched via holes and from etched metal lines. Vias fabricated with this technique exhibit exceptionally low resistance.

Abstract: Methods and apparatuses for encapsulating thermally enhanced (TE) and electrically and thermally enhanced (ETE) integrated circuit assemblies that include bulky thermally conductive heat sinks so as to prevent the formation of pinholes and IC warpage without adding bulk or additional structures. The assemblies are repositioned, through offset in the bonding fingers of the leadframe, so that the rates of mold flow in the two halves of the mold cavity are substantially balanced. The repositioning of the assemblies also substantially balances the amount of mold material in the mold halves to prevent warpage when the IC cools down.

Abstract: The present invention comprises and interrupt controller for use with a programmable digital processor system. The interrupt controller of the present invention includes a plurality of interrupt blocks. The interrupt blocks are used for coupling to a corresponding plurality of peripheral devices. Each of the interrupt blocks are coupled to a data bus included within the interrupt controller. The interrupt controller also includes an interrupt control register. The interrupt control register is coupled to each of the interrupt blocks, and upon receiving an internal interrupt request from any of the interrupt blocks, asserts a processor interrupt request responsive to the internal interrupt request. The interrupt controller includes a processor interrupt request line adapted to couple to a programmable digital processor.

Abstract: The present invention provides connections and methods of restricting an opening. One connection according to the subject invention is configured to restrict a mouth of a container, the mouth having an inner surface having an inside diameter and an outer surface having an outside diameter, the connection includes: a plug having a side surface of varying dimension and configured to engage the inner surface to form a seal of the side surface of the plug and the inner surface; at least one intermediate member having a first end borne by the plug and a second end distally spaced from the first end; and a securing member configured to engage the outer surface of the container and the second end of the intermediate member, the intermediate member being configured to couple the plug and the securing member and maintain the seal of the side surface of the plug with the inner surface of the container.

Abstract: An automated method for selectively locating fill pattern diffusion regions on a semiconductor substrate. In one embodiment, the present invention determines the locations of active diffusion regions on a semiconductor substrate. The present invention also determines the locations of interconnect lines on the semiconductor substrate. Next, the present invention creates a union of the location of the active diffusion regions on the semiconductor substrate and the location of the interconnect lines on the semiconductor substrate. The present invention uses this union to define allowable locations for placement of fill pattern diffusion regions on the semiconductor substrate such that the fill pattern diffusion regions are not disposed under the interconnect lines.

Abstract: An integrated circuit includes a substrate with doped regions, a patterned polysilicon layer defining contacts and local interconnects, a submetal dielectric, a two-metal layer metal interconnect structure with an intermetal dielectric layer, and a passivation layer. Like the dielectric layers, the passivation layer is optically transparent, thick, and planarized. Because of this, laser energy can be directed through the passivation layer to fuse two conductors of the top metal layer without delaminating the passivation layer. In addition, laser energy is directed through the passivation layer and the intermetal dielectric to fuse pairs of conductors in the lower metal layer. Thus, the present invention provides for reliable convenient circuit modification without disturbing dielectric and exposing metal features to moisture and other contaminants.

Abstract: A universal disk controller for microprocessor systems is capable of use as a PCI interface with either SCSI drives or IDE drives. To effect selection of the appropriate one of the IDE or SCSI drives for use with the interface, a configuration logic circuit is coupled with a PCI bus master interface to select an IDE state machine or an SCSI state machine, both of which are coupled with a combined IDE/SCSI interface having common pins for connection to the appropriate IDE or SCSI drive for operation with the controller. Consequently, separate chips for providing interfaces between a PCI bus and either an IDE or an SCSI drive are not required. The system permits switching between IDE and SCSI drives according to the application with which it is being used.

Abstract: A wireless interface for diagnostic examination and programming of vehicular control systems. The wireless interface uses a vehicle processor which is coupled to at least one of a plurality of vehicular control systems. The vehicle processor is used for monitoring and controlling the different vehicular control systems located in the vehicle. A first transceiver is coupled to the vehicle processor for sending and receiving programming signals and operating signals to and from the vehicle processor. A second transceiver is provided for sending the programming signals to the first transceiver and for receiving the operating signals sent from the first transceiver.

Abstract: A system clock signal monitor that monitors a system clock signal by comparing a pulse width of a logic high pulse and a pulse width of a logic low pulse of each system clock duty cycle of the system clock signal to one or more reference clock duty cycles in order to detect any pulse width violations. For each system clock duty cycle, a pulse width violation is detected if the pulse width of a logic high pulse and/or the pulse width of a logic low pulse is equal to or greater than a maximum time interval for the logic high pulse and the logic low pulse. A pulse width violation may also occur if the pulse width of a logic high pulse and/or the pulse width of a logic low pulse is within a risk range (as defined by the system designer) of the maximum time interval for the logic high pulse and the logic low pulse. The system clock signal monitor can be further designed to warn/reset a processor or a user of the processor upon the detection of one or more detected occurrences of a pulse width violation.

Abstract: The present invention provides a computer implemented method and apparatus for determining the total capacitance of a primary interconnect line positioned between top and bottom ground planes. The primary interconnect line is positioned at a distance, H1, from the bottom ground plane and at a distance, H2, from the top ground plane. Preferred embodiments of the present invention include computer implemented processes for empirically determining the total capacitance of the primary interconnect line both with and without neighboring interconnect lines present. Core steps of the present invention include partitioning of a parameter representing fringe capacitance which is due to fringe electric fields induced between sidewalls of the primary interconnect line and the top and bottom ground planes. In the present invention, the fringing capacitance is partitioned into a top fringe capacitance, C.sub.

Abstract: A scalable N-port memory device using as a building block a dual-port memory device core. The dual-port memory has two ports each of which can either serve as a read or a write port. The resulting N-port memory device, besides allowing for design reuse, offers speed, density and cost advantages over conventional N-port memory devices. For example, to realize a 1K word by 128 bit register file memory device having two write ports and either five or six read ports, three dual-port memory device cores are placed in parallel with one another. Each core has separate parallel (dual) read ports. Two write ports are shared in common among all of the cores. The cores are designed to operate at 2X speed, i.e., twice the desired speed of the N-port memory device. A "cycle" at the N-port memory device is composed of two cycles of the underlying 2X speed devices, typically a read cycle followed by a write cycle.