Abstract: An electrostatic chuck device for clamping a semiconductor wafer substrate during processing of the semiconductor wafer includes a power source, at least one negative pole, and a plurality of positive poles. Each positive pole selected from the plurality of positive poles is electrically separated from the negative pole. Also provided is a plurality of fuses, each fuse of the plurality of fuses is coupled to an associated positive pole included in the plurality of positive poles. Each fuse is further coupled to the power source. In some embodiments, each positive pole is electrically separated from the negative pole by an insulating epoxy. In other embodiments, the plurality of positive poles are connected to each other in parallel.

Abstract: A multiple processor circuit arrangement utilizes a master processor which controls the operational state of a slave processor by programming internal control registers on the slave processor. In addition, a stack-based processor utilizes a stack cache for accelerating stack access operations and thereby accelerating the overall performance of the processor. When the stack-based processor is utilized as a slave processor in the aforementioned master/slave multi-processor computer system the slave processor is optimized to process platform-independent program code such as Java bytecodes, thereby permitting fast and efficient execution of both program code native to the master processor as well as platform-independent program code that is in effect native to the slave processor.

Abstract: A semiconductor wafer polishing method comprises forming at least one alignment mark within an alignment area on a semiconductor wafer, forming a layer to be polished over the wafer, the layer being formed to be generally elevationally higher proximately about and surrounding the alignment area than within the alignment area, and polishing the layer. According to another aspect, a semiconductor wafer includes an alignment marking area formed relative to a surface of the wafer. At least one alignment mark is provided within the alignment area. A structure is formed about the alignment marking area and extends from the wafer surface a greater elevation than any elevation from such surface from which the alignment mark extends. Furthermore, a layer of material to be polished is provided over the structure to cause the material to be polished to be elevationally higher over the structure than over the alignment mark.

Abstract: A FIFO controller circuit for interfacing data from a device running at one clock speed so that it is compatible with another device or transmission medium running at a different clock speed. A write controller is used to control the writing of data into the FIFO. The write controller is clocked at a first clock speed. A read controller is used to control the reading of data from the FIFO at a second, different clock speed. A counter is incremented when data is written to the FIFO and decremented when data is read from the FIFO. Thereby, the counter represents an amount of memory within the FIFO that is currently available. The decrement signal is generated in the first clock domain and then synchronized to the second clock domain. This provides error-free interfacing, irrespective of any phase differences existing between the two clock signals.

Abstract: A method for laying out an integrated circuit design based upon a netlist provided by a behavioral synthesis tool includes the steps of: (a) placing cells specified by the netlist in a layout area in a placement step, the cells including pins that are interconnected by nets; (b) verifying timing constraints in a timing verification step of the placed cells in the layout area; and (c) if the timing verification step indicates that timing does not verify in that the timing constraints are not met: (i) modifying the netlist pursuant to an engineering change order (ECO); and (ii) making an ECO placement of at least one cell into the layout area based upon the timing constraints while adjusting any affected nets as specified by the netlist. A layout tool implements the method on a computer system to form a portion of and integrated circuit fabrication system.

Abstract: A system that enables a portable station of the personal handy phone system to support a conference call. The present invention provides this capability by empowering a portable station to communicate with up to four cell stations simultaneously enabling the user of the portable station to communicate with the users of four other telecommunication devices. Specifically, the present invention modifies the internal circuitry of a portable station to increase the number of receiving channel circuits to four and the transmitting channel circuits to four while adding a digital signal processor to mix the different received and outgoing voice signals. The increased number of receiving and transmitting channel circuits enables a portable station to utilize all the communication slots located within the frames of the radio communication interface of the personal handy phone system. Communication is time-multiplexed across these slots.

Abstract: The present invention allows the behavior of a state machine to be readily modified by software after it has been fabricated in silicon. To perform these modifications, the present invention uses special patch registers, multiplexers, and comparators to bypass certain states within the sequence of states within the combinatorial logic of the state machine and/or add new state sequences. Each patch register stores a state to be patched, a next state, and outputs. The state to be patched is the state that will be modified, while the next state is the state the state machine transitions into from the state to be patched, and the outputs are the outputs generated and asserted by the state machine while within the next state. Many such patch registers can be used by the present invention to define many modifications. Using this patch mechanism, the present invention allows new states to be added and existing states to be removed from the sequence of states that the state machine cycles through.

Abstract: A test socket for ball grid array packages (BGA) for integrated circuits is described. The socket includes a basket or cradle shaped to receive the balls of the BGA in individual electrically conductive receptacles. The receptacles have flexible walls and an elastomer disposed outside the walls. The BGA, carrying the balls is urged in a direction parallel to the plane of the BGA thereby carrying the basket in the same direction. A stop is provided to limit the movement of the basket so that further movement of the BGA causes compression of the elastomer so as to provide an electrical connection between each ball and its associated receptacle despite any minor differences in the sizes or locations of the individual balls. Means are provided for connecting each of the receptacles to an external circuit.

Abstract: The present invention provides a nominal temperature and process compensating bias circuit for an integrated circuit. The bias circuit comprises a current source, a pair of linear devices, and a current stage. The current source generates a bias current. The pair of linear devices includes a first linear device and a second linear device. The first and second linear devices are coupled to each other and to the current source at a common node to enable the bias current from the current source to flow through the linear devices. The current stage includes a first transistor and a second transistor with the first transistor being coupled to the first linear device at the drain node of the first transistor and the second transistor being coupled to the second linear device at the drain node of the second transistor.

Abstract: An arrangement for transferring information between initiating and target buses, using contiguous command buffering and target bus command decoding. A bus interface bridge circuit includes an initiating bus interface which outputs a plurality of commands, where each of the commands includes a corresponding code. A memory queue is coupled to the initiating bus interface to receive the commands, and to contiguously store the commands into the registers of the queue. A target bus interface is coupled to the output of the memory queue to successively receive the commands. The commands are then executed at targeted devices in accordance with their corresponding codes. A method for transferring commands from an initiating bus to a target bus using contiguous command buffering and target bus command decoding is also provided.

Abstract: A sharp transition or step is first formed on the surface of a semiconductor material. A layer of interconnect metal is deposited by conformal CVD and substantially the same thickness of the metal as deposited is removed by anisotropic etching, leaving a narrow line of the interconnect metal at the step portion to serve as an interconnect line. Interconnect lines of 0.5 micron or below can be achieved since the process is not limited by photostepper resolution.

Abstract: The present invention comprises a ringer interface circuit for generating a ringer signal for controlling a telephone ringer. The circuit of the present invention includes a first frequency divider, a second frequency divider, and a third frequency divider. The first frequency divider is adapted to receive a ringer clock signal and generate a first divider frequency output therefrom. The second frequency divider is coupled to receive the first divider frequency output and is adapted to generate a second divider frequency output using the first divider frequency output. The second frequency divider is further adapted to generate a oversampled audio frequency signal. The third frequency divider is coupled to receive the second frequency divider output and is adapted to generate a period signal using the second frequency divider output.

Abstract: A shallow trench isolation structure and method for forming such structure. In one embodiment, the semiconductor device isolating structure of the present invention includes a trench formed into a semiconductor substrate. A cross-section of the trench has a first sidewall sloping inwardly towards the center of a substantially planar bottom surface, and a second sidewall sloping inwardly towards the center of the substantially planar bottom surface. Additionally, a cross section of the trench has a first rounded bottom trench corner at an interface of the first sidewall and the substantially planar bottom surface, and a second rounded bottom trench corner at an interface of the second sidewall and the substantially planar bottom surface.

Abstract: A method and computer system for automatically determining test patterns for a netlist having multiple clocks and sequential circuits. The invention utilizes a static model of a sequential circuit and models the sequential circuit having multiple clock signals (e.g., one model is used for all multiple clock signals). The multiple clock signals include primary clock input signals and internal clock signals. The clock signals can be gated or dual edge. The invention makes use of the "iterative array representation of sequential circuits" (IAR) model for automatic test pattern generation (ATPG) but utilizes a static sequential circuit model. The invention receives user defined input clock signal waveforms and determines a cycle of clocks based thereon that statically represents all waveforms over time. The cycle of clocks is divided into frames where each frame contains stable clock values.

Abstract: A scan data flip-flop having improved timing characteristics is provided. A scan flip-flop includes: a first data input coupled with a first latch; a second data input coupled with said first latch; a clock input coupled with said first latch; a data control input; and a data controller operably coupled with said clock input and said data control input and said first latch; said data controller being configured to generate an enable signal responsive to a clock signal from said clock input and a data control signal from said data control input, and said enable signal to control the input of data into said first latch. The normal or first data input signal is preferably directly applied to the first latch within the scan data flip-flop according to the present invention. The data controller of the scan data flip-flop according to the present invention is preferably void of a multiplexer. A method for controlling the entry of data into a scan data flip-flop is also provided.

Abstract: A translating circuit coupled to a processor and memory of a computer system translates platform-independent instructions such as Java bytecodes into corresponding native instructions for execution by the processor. In one embodiment, the translating circuit is incorporated into the same integrated circuit device as the processor. In another embodiment, the translating circuit is provided within one or more external integrated circuit devices. One or more look-up tables map platform-independent instructions into one or more native instructions for the processor, thereby minimizing software-based interpretation of platform-independent program code. Moreover, platform-independent instructions are mapped to native instructions on-the-fly, or alternatively, in blocks prior to execution using a state machine.

Abstract: A CMOS super high speed voltage controlled oscillator (VCO) circuit that operates at frequencies of at least 3 GHz. The VCO circuit of the present invention includes a replica circuit, a first VCO cell coupled to the replica circuit, and a second VCO cell coupled to the first VCO cell and the replica circuit. A VCO output for transmitting a VCO output signal is also included. A first current source is coupled to the first VCO cell to transmit a first current from the power supply to the first VCO cell. A second current source is coupled to the second VCO cell to transmit a second current from the power supply to the second VCO cell. The first VCO cell and the second VCO cell each have respective first and second source follower load transistors coupled to the replica circuit. In addition, the first and second VCO cells, the first and second current sources, and the replica circuit are all fabricated using n-channel MOS transistors.

Abstract: A PTAT current source comprising a first branch including a bipolar transistor structure connected in diode configuration, and first and second sub-branches coupled to the bipolar transistor structure, the first sub-branch including a p-channel MOSFET transistor connected in diode configuration and an n-channel MOSFET transistor which is not connected in diode configuration, and the second sub-branch including a p-channel MOSFET transistor not connected in diode configuration and an n-channel MOSFET transistor connected in diode configuration; and a second branch including a bipolar transistor structure connected in diode configuration, and third and fourth sub-branches coupled to the bipolar transistor structure, the third sub-branch including a p-channel MOSFET transistor connected in diode configuration and an n-channel MOSFET transistor which is not connected in diode configuration, and the fourth sub-branch including a p-channel MOSFET transistor not connected in diode configuration and an n-channel MOSF

Abstract: A testing apparatus and method are for testing a plurality of logic blocks within an integrated circuit. The integrated circuit includes a test data input bus, a test data output bus coupled to the output of each logic block, and test enable means which includes selection means coupled between the plurality of logic blocks and the test data input bus. The test enable means selects a first logic block from the plurality of logic blocks, and the selection means selectively inputs to each logic block either normal operating input or the test data. The test results are received from the first logic block through the test data output bus.

Abstract: The present invention comprises a noise insensitive current source circuit having a high power supply rejection ratio. The circuit of the present invention is for use with noise sensitive circuits. The circuit of the present invention includes a first reference current source, a second reference current source, and a first, second, third, and fourth transistor. The first transistor has a drain coupled to a power supply and a source coupled to a ground via the first reference current. The second transistor has a drain coupled to the power supply and a source coupled to ground via the second reference current source. The gate of the second transistor is coupled to the gate of the first transistor and to the source of the first transistor. A third transistor has a drain coupled to the power supply and a source coupled to ground via the second reference current source. The gate of the third transistor is coupled to the source of the second transistor.