Patents Assigned to VLSI Technology, Inc.
  • Patent number: 6207543
    Abstract: A process for making an integrated circuit is disclosed. This technique includes electrically interconnecting a pair of adjacent transistors positioned along a semiconductor substrate by coating with an oxide layer, planarizing the layer, then forming a trench exposing a contact region for each transistor. This trench is filled with a metal, such as tungsten to provide an electrical interconnection of the contact regions. The metal is then planarized to be approximately coplanar with the planarized oxide layer. Metal gate electrodes are formed at the same time as the interconnection. Additional processing includes depositing an IMO layer over the planarized metal and oxide and defining additional interconnections through the IMO layer.
    Type: Grant
    Filed: June 30, 1997
    Date of Patent: March 27, 2001
    Assignee: VLSI Technology, Inc.
    Inventors: Ian Robert Harvey, Xi-Wei Lin
  • Patent number: 6208172
    Abstract: A circuit monitor performance of an integrated circuit. The circuit includes a clock signal and a phase delay detection circuit. The clock signal is used by the integrated circuit to generate an output signal on an output pin of the integrated circuit. The phase delay detection circuit detects relative phase difference between the clock signal and the output signal on the output pin of the integrated circuit. The phase delay detection circuit includes a digital signal generator and an integrator. The digital signal generator is connected to an output pin of the integrated circuit. The digital signal generator generates a digital signal. Changes in phase delay between the output signal on the output pin of the integrated circuit and the clock signal used by the integrated circuit are encoded in a duty cycle of the digital signal generated by the digital signal generator. The integrator is connected to the digital signal generator and integrates the digital signal to produce an integrated signal.
    Type: Grant
    Filed: January 13, 1995
    Date of Patent: March 27, 2001
    Assignee: VLSI, Technology, Inc.
    Inventors: David R. Evoy, Nicholas J. Richardson
  • Patent number: 6202172
    Abstract: The present invention comprises a smart debug interface circuit for the diagnostic testing and debugging of a software application for a programmable digital processor system. The smart debug interface circuit of the present invention includes an instruction register for coupling to an instruction bus of a programmable digital processor. The instruction register is adapted to drive instructions onto the instruction bus. The instruction register couples to the instruction bus in a parallel manner. The smart debug interface circuit of the present invention includes a data register for coupling to a data bus of the programmable digital processor. The data register is adapted to read data from the data bus and couples to the data bus in a parallel manner. The instruction register and data register are each coupled to an interface port. The interface port couples the smart debug interface circuit to a host computer system.
    Type: Grant
    Filed: June 10, 1998
    Date of Patent: March 13, 2001
    Assignee: VLSI Technology, Inc.
    Inventor: Christian Ponte
  • Patent number: 6198294
    Abstract: Thickness of a wafer is monitored during grinding. A conductive plate is located below the wafer during grinding. One or more capacitive sensors are located above the wafer during grinding. A monitoring device monitors capacitance of the conductive plate and the capacitive sensor.
    Type: Grant
    Filed: May 17, 1999
    Date of Patent: March 6, 2001
    Assignee: VLSI Technology, Inc.
    Inventor: Andrew J. Black
  • Patent number: 6199031
    Abstract: An interface system for testing and verifying the design of an ASIC at different levels of abstraction, wherein the ASIC includes a logic entity and a processor entity. The system of the present invention is embodied as software which executes within a computer system. The software, when executed by the computer system, causes the computer system to implement a model of the ASIC, a simulator, and a test interface. The model of the ASIC is embodied in HDL (Hardware Description Language) and includes a logic entity and a processor entity. The simulator is adapted to test the model. The test interface interfaces the model with the simulator. The test interface includes a simulator portion and a model portion. The simulator portion is coupled to the simulator. The model portion is embodied in HDL and is coupled to both the logic entity and the processor entity. The model portion and the simulator portion are coupled to exchange information.
    Type: Grant
    Filed: August 31, 1998
    Date of Patent: March 6, 2001
    Assignee: VLSI Technology, Inc.
    Inventors: Pierre Yves Challier, Christelle Faucon, Jean Francois Duboc
  • Patent number: 6196900
    Abstract: The present invention is an ultrasonic transducer slurry dispensing device and method for efficiently distributing slurry. The present invention utilizes ultrasonic energy to facilitate efficient slurry application in a IC wafer fabrication process to permits reduced manufacturing times and slurry consumption during IC wafer fabrication. In one embodiment a chemical mechanical polishing (CMP) ultrasonic transducer slurry dispenser device includes a slurry dispensing slot, a slurry chamber coupled and an ultrasonic transducer. The slurry chamber receives the slurry and transports it to the slurry dispensing slots that apply slurry to a polishing pad. The ultrasonic transducer transmits ultrasonic energy to the slurry.
    Type: Grant
    Filed: September 7, 1999
    Date of Patent: March 6, 2001
    Assignee: VLSI Technology, Inc.
    Inventors: Liming Zhang, Samuel Vance Dunton, Milind Ganesh Weling
  • Patent number: 6198306
    Abstract: A CMOS wave shaping buffer circuit comprises two CMOS inverter stages connected as a non-inverting buffer. In addition, the two stages are further coupled by way of their supply connections to produce a positive feedback from the second stage to the first whenever both stages are driven to a linear state, that is both transistors of each stage are “ON”. The positive feedback prevents the output stage from remaining in a logically ambiguous state, but forces crisp transitions from one state to another even for slowly changing input signals.
    Type: Grant
    Filed: July 24, 1998
    Date of Patent: March 6, 2001
    Assignee: VLSI Technology, Inc.
    Inventor: D. C. Sessions
  • Patent number: 6197621
    Abstract: An integrated circuit includes a substrate with doped regions, a patterned polysilicon layer defining contacts and local interconnects, a submetal dielectric, a two-metal layer metal interconnect structure with an intermetal dielectric layer, and a passivation layer. Like the dielectric layers, the passivation layer is optically transparent, thick, and planarized. Because of this, laser energy can be directed through the passivation layer to fuse two conductors of the top metal layer without delaminating the passivation layer. In addition, laser energy is directed through the passivation layer and the intermetal dielectric to fuse pairs of conductors in the lower metal layer. Thus, the present invention provides for reliable convenient circuit modification without disturbing dielectric and exposing metal features to moisture and other contaminants.
    Type: Grant
    Filed: June 18, 1999
    Date of Patent: March 6, 2001
    Assignee: VLSI Technology Inc.
    Inventor: Ian R. Harvey
  • Patent number: 6198784
    Abstract: The present invention provides methods of synchronization, personal handy-phone system stations, and phase lock loops. Synchronization of a personal handy-phone system station with a telecommunication network, and another communication station are provided. One method of synchronization comprises: providing a counter configured to generate a plurality of counter values; storing a first counter value; detecting a reference event; latching a second counter value responsive to the detecting of the reference event; comparing the first counter value and the second counter value to detect phase drift; and compensating for phase drift responsive to the comparing.
    Type: Grant
    Filed: October 20, 1999
    Date of Patent: March 6, 2001
    Assignee: VLSI Technology, Inc.
    Inventors: Denis Archambaud, Patrick Feyfant, Philippe Gaglione, Varenka Martin, Oliver Weigelt, Laurent Winckel, Satoshi Yoshida
  • Patent number: 6190236
    Abstract: The present invention is a vacuum removal system for removing polishing by-products from the surface of a polishing pad in a chemical mechanical polishing (CMP) machine used to polish wafers. The vacuum removal system includes a vacuum removal nozzle which is adapted to dislodge and remove polishing by-product particles from a textured surface of a polishing pad through the application of suction. The vacuum removal nozzle is connected to a mounting attachment. The mounting attachment is mounted on the polishing machine and is adapted to maintain close proximity of the vacuum removal nozzle with the textured surface of the polishing pad. A vacuum line is connected to the vacuum nozzle to convey a vacuum to the vacuum nozzle and to receive the polishing by-product particles from the vacuum nozzle. A vacuum source is connected to the vacuum line to generate the vacuum used by the system.
    Type: Grant
    Filed: October 16, 1996
    Date of Patent: February 20, 2001
    Assignee: VLSI Technology, Inc.
    Inventor: Charles Franklin Drill
  • Patent number: 6188257
    Abstract: Power-on-reset logic is included within an integrated circuit. The power-on-reset logic includes a power-on-reset cell. The power-on-reset cell causes a reset signal to be issued upon a power signal being connected to the integrated circuit. The power-on-reset cell includes a power down input connected to a power-down line. When a power-down signal is placed on the power-down line, the power-on-reset cell is inactivated so that the power-on-reset cell does not cause the reset signal to be issued upon the power signal being connected to the integrated circuit. The power-on-reset logic also includes a logic block connected to the power-down line and to a system clock. The logic block issues a reset when the power-down signal is placed on the power-down line and the system clock is active. For example, the logic block is a delay (D) flip-flop having a D input connected to the power down line and a clock input connected to the system clock.
    Type: Grant
    Filed: February 1, 1999
    Date of Patent: February 13, 2001
    Assignee: VLSI Technology, Inc.
    Inventor: Mark Leonard Buer
  • Patent number: 6184119
    Abstract: A method is provided for reducing contact resistances in semiconductors. In the use of fluorocarbon plasmas during high selectively sub-quarter-micron contact hole etching, with the silicon dioxide(SiO2)/silicon nitride(Si3N4)/silicide(TiSix) layers, polymerization effects have been discovered to be crucial. The process includes using a high etch selective chemistry, to remove SiO2 first, then switching to another chemistry with high selectivity of Si3N4-to-TiSix. To obtain good etch selectivity of SiO2-to-Si3N4, fluorocarbon plasmas containing high C/F ratio are employed. This results in the formation of reactive unsaturated polymers which stick easily to contact hole sidewalls and bottoms. Fluorine from the polymer was discovered to severely degrade the etch selectivity of Si3N4-to-TiSix. Different polymer removing methods to restore etch selectivity of Si3N4-to-TiSix are provided which can be applied to any highly selective etching of oxide versus nitride.
    Type: Grant
    Filed: March 15, 1999
    Date of Patent: February 6, 2001
    Assignee: VLSI Technology, Inc.
    Inventors: Victor Ku, Delbert Parks
  • Patent number: 6185147
    Abstract: A method and apparatus for programmable read only memory with high speed differential sensing at low operating voltage. In one embodiment, a programmable memory cell is comprised of word line, a bitline, and a transistor. The transistor, representing a single binary digit (bit), has a gate coupled to a word line, a drain coupled to a bitline, and a source capable of being programmed to provide a logic level of 0 and a logic level of 1. By programming the source of the transistor, the bitline approximately equal capacitance for both logic level 0 and logic level 1 states.
    Type: Grant
    Filed: January 4, 2000
    Date of Patent: February 6, 2001
    Assignee: VLSI Technology, Inc.
    Inventor: Kwo-Jen Liu
  • Patent number: 6182264
    Abstract: A dynamic error correction system for a bi-directional digital data transmission system. The transmission system of the present invention includes a transmitter adapted to encode information into a signal. A receiver receives the signal and decodes the information encoded thereon. The signal is transmitted from the transmitter to the receiver via a communications channel. A signal quality/error rate detector is coupled to the receiver and is adapted to detect a signal quality and/or an error rate in the information transmitted from the transmitter. The receiver is adapted to implement at least a first and second error correction process, depending upon the detected signal quality/error rate. The first error correction process is more robust and more capable than the second error correction process. The receiver coordinates the implemented error correction process with the transmitter via a feedback channel.
    Type: Grant
    Filed: May 22, 1998
    Date of Patent: January 30, 2001
    Assignee: VLSI Technology, Inc.
    Inventor: Stefan Ott
  • Patent number: 6177703
    Abstract: Accordingly, exemplary embodiments of the present invention are directed to single poly flash EEPROM cells which avoid the drawbacks of conventional two poly stacked gate cells, and which are easily integrated with high performance logic technologies. An exemplary two transistor flash-EEPROM memory cell array comprises a plurality of these flash EEPROM cells, each having a select transistor with a bit line and a word line, where the select transistor is in series with a floating gate transistor. The floating gate transistor has a thin tunneling oxide formed on a textured monocrystalline substrate. The floating gate is also formed over a heavily doped region in the substrate which forms a coupling line capacitively coupled to the floating gate, and which performs a tunneling function.
    Type: Grant
    Filed: May 28, 1999
    Date of Patent: January 23, 2001
    Assignee: VLSI Technology, Inc.
    Inventor: James A. Cunningham
  • Patent number: 6178478
    Abstract: A system and method for preventing address aliasing when using a single address cycle to transmit a target address in a computer system that includes target devices having addresses of different ranges. The computer system comprises a bus, an initiator device coupled to the bus, a first target device coupled to the bus, and a second target device coupled to the bus. The first target device has a first address range comprising a plurality of bits, and the second target device has a second address range comprising a fewer number of bits than the first address range. The initiator device transmits a signal indicating the size of the target address and also separately transmits in a single address cycle the target address. The second target device disables its address decode logic in response to the signal from the initiator device provided that the size of the target address is greater than the second address range.
    Type: Grant
    Filed: December 11, 1998
    Date of Patent: January 23, 2001
    Assignee: VLSI Technology, Inc.
    Inventors: Peter Chambers, Subramanian S. Meiyappan, Swaroop Adusumilli
  • Patent number: 6178477
    Abstract: The present invention comprises a system for implementing pseudo delayed transactions through a bridge in order to guarantee access to a shared device. The system of the present invention functions in a computer system having a plurality of busses, including a first bus on one side of a bridge and a second bus on another side of the bridge. A first initiator device and a second initiator device are coupled to the first bus. The first and second initiator devices are both adapted to request ownership of the first bus and receive a respective first and second grant signal responsive thereto. A target device is coupled to the second bus. The bridge is coupled to the first bus and the second bus. The bridge is adapted to implement data transactions between the target device and the first device or the second device.
    Type: Grant
    Filed: October 9, 1997
    Date of Patent: January 23, 2001
    Assignee: VLSI Technology, Inc.
    Inventors: Ken Jaramillo, Carl Knudsen
  • Patent number: 6176983
    Abstract: The present invention provides methods of forming a semiconductor workpiece. One method of forming a semiconductor device in accordance with the present invention includes: providing a semiconductor workpiece; forming a via within the semiconductor workpiece, the via including plural sidewalls joining a bottom surface at respective plural corners; first sputtering a process layer upon at least a portion of the bottom surface using ionized metal plasma physical vapor deposition; and following the sputtering of the process layer, second sputtering at least some of the process layer towards the corners within the via.
    Type: Grant
    Filed: September 3, 1997
    Date of Patent: January 23, 2001
    Assignee: VLSI Technology, Inc.
    Inventors: Subhas Bothra, Dipankar Pramanik, Samit Sengupta
  • Patent number: 6173436
    Abstract: A method of designing a reset circuit for a digital integrated circuit (IC) layout is described. The reset circuit is designed with the intention of making it visually non-detectable in the digital IC layout by implementing the reset circuit entirely in digital elements and then using standardized digital layout cells and routing such that the reset circuit is essentially non-discernible from the digital circuitry of the IC device layout. In addition, circuit elements are designed using devices having dimensions that are essentially the same as typical digital devices in the digital IC layout.
    Type: Grant
    Filed: October 24, 1997
    Date of Patent: January 9, 2001
    Assignee: VLSI Technology, Inc.
    Inventors: John C. Ciccone, Bing L. Yup
  • Patent number: 6172923
    Abstract: A method and apparatus for programmable read only memory with high speed differential sensing at low operating voltage. In one embodiment, a programmable memory cell is comprised of word line, a bitline, and a transistor. The transistor, representing a single binary digit (bit), has a gate coupled to a word line, a drain coupled to a bitline, and a source capable of being programmed to provide a logic level of 0 and a logic level of 1. By programming the source of the transistor, the bitline approximately equal capacitance for both logic level 0 and logic level 1 states.
    Type: Grant
    Filed: January 4, 2000
    Date of Patent: January 9, 2001
    Assignee: VLSI Technology, Inc.
    Inventor: Kwo-Jen Liu