Abstract: The method implements implicit sequential behavior using a general finite state machine architecture (FSM) through the systematic evaluation of control flow graphs (CFGs) having one or more weight statements which are sensitive to the same unique clock edge. Each of the weight statements contained in the CFG are assigned a state in the state machine. All of the executable paths between each weight statement are fully evaluated on a node-by-node basis. From this evaluation process, expressions are extracted which define combinational logic necessary to produce additional inputs to the FSM to produce the next state, as well as expressions representing outputs of the FSM as associated with each transition from one state to another. The method also deals with proper evaluation of unrollable loops.

Abstract: The present invention is a system and method for implementing peripheral device bus mastering in a mobile computer system. The system uses the micro-controller of the mobile computer system to program a DMA controller. The DMA controller transfers data to and from the memory of the mobile computer system. A bus controller which is coupled to both the micro-controller and the DMA controller implements a memory data transfer request from the DMA controller and the micro-controller. A device controller, either a IDE hard disk controller or an ECP parallel port controller, is also coupled to the DMA controller and the micro-controller. The device controller receives and responds to the command signals from the micro-controller by transferring data to and from the DMA controller means and generating a completion signal when the transfer is complete.

Abstract: A system for altering a clock frequency to a logic controlling device that controls logic which runs at a fixed frequency slower than a frequency of a computer system running the logic. The system speeds up the clock signal to a logic controller when the logic controller is arbitrating between different operational requests. When the logic controller acknowledges a specific operational request, the clock controller immediately slows the clock signal down in order to allow a command strobe length that the logic device executing a specific operation request requires.

Abstract: A zero-run-length encoder for a JPEG compression system comprises an addressable memory for storing 63 input values (quantized AC DCT coefficients), zero-detection logic, a shift register, a value generator, an accumulator, a Huffman encoder, done-detection logic, and last-value-detection logic. For each input value, the zero-detection logic stores zero/nonzero indications in a respective bit position of the shift register. The value generator includes a leading-zero counter that determines the number of leading zeroes in the leading fifteen bit positions of the shift register. This count is used to determine an offset value which is added to a previous address value (initially zero) to yield a present address value. The present address value is used to select a memory location from which an input value is read from memory into the Huffman encoder. The Huffman encoder generates an output code as a function of the addressed input value and the leading zero count.

Abstract: The present invention relates to a system that can combine data packets from two serial data streams to provide a single uncorrupted serial data output. The system is comprised of an internal data source and an external data source which each generates serial bit packets containing system information. The outputs of both the internal and external sources are coupled to a packet arbiter which combines the serial bit packet from the internal data source with the serial bit packet from the external data source to form an uncorrupted combined serial data output stream.

Abstract: A method of designing a circuit is described. A netlist for a circuit is generated. An analysis of the netlist is then executed to generate a set of cell instance performance values that characterize the performance of multiple gate instance-level components of the circuit in view of a selected parameter, such as circuit timing, circuit power consumption, or circuit area. Relying upon the set of cell instance performance values, a problematic component within the circuit is identified for replacement. A set of functionally equivalent candidate components are then identified. Each candidate component is analyzed with respect to the selected parameter. The analysis identifies an optimally performing candidate component. An instance of the optimally performing candidate component is then substituted into the netlist for the problematic component to improve the performance of the circuit.

Abstract: An interstage amplifier for a pipelined analog-to-digital converter comprises an operational amplifier (50) having two balanced amplifying paths; a first pair of capacitors (55,58); a second pair of capacitors (56,57); and switching means (59-62) connected to the capacitors and said amplifier and arranged for: (i) during a first phase, enabling the first pair of capacitors (55,58) to receive a respective first sample of a first signal; (ii) during a second phase, enabling the second pair of capacitors (56,57) to receive a second sample of the first signal; (iii) during a third phase, enabling the first pair of capacitors (55,58) to receive a first sample of a second or reference signal and to enable charge to be transferred from each of the first pair of capacitors by way of a respective path of the amplifier to a respective one of the second pair of capacitors; and (iv) during a fourth phase, enabling the second pair of capacitors (56,57) to receive a second sample of the said second or reference signal and

Abstract: A metal layer on an integrated circuit includes active signal lines and fill metal segments. The fill metal segments are polygons. Each fill metal segment at its narrowest has a width which is not greater than 1.25 times a design rule metal pitch for a technology used to fabricate the integrated circuit. In addition, each fill metal segment is separated from every other fill metal segment by spacing which is at least 0.7 times the design rule metal pitch for the technology used to fabricate the integrated circuit. Also, each fill metal segment is separated from every active signal line by spacing which is at least 0.5 times the design rule metal pitch for the technology used to fabricate the integrated circuit.

Abstract: The invention relates to MOS devices and methods for fabricating MOS devices having multilayer metallization. In accordance with preferred embodiments, internal passivation is used for suppressing device degradation from internal sources. Preferred devices and methods for fabricating such devices include formation of one or more oxide layers which are enriched with silicon to provide such an internal passivation and improve hot carrier lifetime. Preferred methods for fabricating MOS devices having multi-level metallization include modifying the composition of a PECVD oxide film and, in some embodiments, the location and thickness of such an oxide. In an exemplary preferred embodiment, PECVD oxide layers are modified by changing a composition to a silicon enriched oxide.

Abstract: A particle removal wafer including ridges defining recessed areas and sticky material placed in these recessed areas can be run through wafer processing equipment. The particle removal wafer can remove particles that would otherwise adhere to the backs of wafers run through this equipment. Particles adhering to the backs of wafers are a problem in the photolithographic steps. These particles cause the focus of the photolithographic system to be off and thus can cause fatal errors. By removing the particles which could adhere to the backs of wafers from the wafer fabrication equipment, the accuracy of the photolithographic process can be improved.

Abstract: A resistive load structure and method for making a resistive load structure for an integrated circuit includes the use of an amorphous silicon "antifuse" material. The resistive load structure can be used in an SRAM cell to provide a load to counteract charge leakage at the drains of two pull-down transistors and two pass transistors of the SRAM cell. The resistive load structure is advantageously formed by depositing an amorphous silicon pad over a conductive via, and the resistance of the resistive load structure is controlled by adjusting the thickness of the amorphous silicon pad and varying the diameter of the underlying conductive via.

Abstract: A method for preventing deadlocks is used in a computing system in which a host bus is connected to a first input/output bus through a first bridge and the first input/output bus is connected to a second input bus through a second bridge. When transferring data from a first input/output device on the second input/output bus to a memory on the host bus, the first input/output device requests mastership of the second input/output bus. Before granting mastership to the first input/output device, the second bridge instructs the first bridge to flush and disable write buffers within the first bridge. After the write buffers have been flushed, the first input/output device is granted mastership of the second input/output bus. The second bridge requests mastership of the first input/output bus by asserting a request signal on a request line. The first bridge then obtains mastership of the host bus in order to allow the transfer of the data from the first input/output device to the memory.

Abstract: A method for monitoring contamination in a semiconductor wafer uses a capacitance-frequency measurement on MOS structures to calculate an impurity concentration. The silicon substrate along with an oxide layer is first biased into the inversion region using a variable frequency waveform generator superimposed upon a DC voltage bias. Next, the capacitance of the wafer is measured as a function of the varying frequency in order to develop a capacitance versus frequency curve. From this frequency response, a bandwidth (BW) is measured at a particular normalized capacitance point. The impurity concentration N is then derived using the formula N=G.times.BW, where G is the correlation constant. With an a priori knowledge of impurity concentration, N, the constant G may be derived by measuring a bandwidth of the capacitance versus frequency curve. Once the constant G is determined, future evaluation of impurity concentration can be made by a capacitance measurement.

Abstract: A deadlock detection and resolution circuit for resolving a deadlock condition in a bridge circuit coupled to a memory, a host bus and a PCI bus of a computer system. The host bus and the PCI bus are configured to operate concurrently and asynchronously. The bridge circuit includes a host master circuit and a PCI slave circuit coupled between the host bus and the PCI bus and configured to service a PCI-MEMORY instruction from an external PCI master coupled to the PCI bus. A PCI master circuit and a host slave circuit within the bridge circuit couples between the PCI bus and the host bus and configured to service a CPU-PCI transaction from a CPU coupled to the host bus. The aforementioned deadlock condition occurs when the PCI-MEMORY transaction proceeds simultaneous with an issuance of the CPU-PCI transaction. The deadlock detection and resolution circuit includes first circuit for asserting an asynchronous handshake signal to the PCI slave of the bridge circuit.

Abstract: A technique for forming a high-performance sub-half micron MOS transistor is disclosed which has improved short channel characteristics without degradation of device performance. The transistor comprises a semiconductor substrate, a gate electrode, graded source and drain impurity regions, a first set of gate sidewall spacers, and a second set of gate sidewall spacers. The graded source and drain impurity regions comprise a relatively linear continuum of doped regions, ranging from lightly doped (LDD) regions, to moderately doped (MDD) regions, to heavily doped regions. Additionally, the transistor may include a punch through barrier region located within the substrate under the gate electrode. With these features, the transistor of the present invention allows for more precise control of conduction channel length without degradation of either (1) body factor and current drive, and/or (2) junction leakage, and without compromising hot carrier immunity.

Abstract: A digital communication system including a digital controller (11), a master circuit (14) capable of communicating in a variety of serial protocols, and at least one slave circuit (16). The digital controller is preferably a microprocessor. The master circuit is configured in a selected serial protocol by the digital controller in response to data words provided by the digital controller. The slave circuit is connected to the master circuit and communicates in the master circuit's selected serial protocol under the control of data words sent from the digital controller to the master circuit. The master circuit is a bi-directional, parallel-to-serial and serial-to-parallel interface circuit having three programmable channels (CHANNEL 0, 1, 2).

Abstract: A system for film thickness sample assisted surface profilometry. The sample assisted surface profilometry system of the present invention is utilized to determine an absolute topography variation of a surface of a layer of an integrated circuit with respect to the surface of an underlying layer of known height orientation. The present invention is comprised of a thickness measurement tool for measuring a thickness of the layer at sample points. The thickness measurement tool measures a thickness sample, wherein the thickness sample characterizes the thickness of the layer over the known layer. A surface profilometry tool is coupled to the thickness measurement tool to receive the thickness measurements of the sample points. The surface profilometry tool is utilized to measure relative topography variations of the surface of the layer.

Abstract: The present invention relates to a system and method for dynamically altering the speed of a bus based on utilization of the bus. The system will monitor a bus for a predetermined number of clock cycles. The system will then lower the frequency that the bus runs at if the bus is underutilized, or the system will increase the frequency that the bus runs at if the bus is at or nearing saturation.

Abstract: Power is conserved in a computing system by detecting when a user's hands are not placed over a keyboard for the computing system. When it is detected that the user's hand are not placed over the keyboard power to a display for the computing system is reduced. For example, the hands are detected by generating and detecting ultrasound waves. In one embodiment of the present invention, the ultrasound waves are generated and detected from positions on a case of the computing system so that when the user's hands are placed on the keyboard, the user's hands block a portion of the ultrasound waves from being detected. In another embodiment, the ultrasound waves are generated and detected from positions on a case of the computing system so that when the user's hands are placed on the keyboard, the user's hands reflect a portion of the ultrasound waves so that the portion of the ultrasound waves are detected.

Abstract: A metastableproof flip-flop receives an input value on a flip-flop input. The flip-flop holds an output value on a flip-flop output. In response to a transition of a clock signal, a transition in the output value occurs. The new output value is the input value formerly received by the flip-flop. In order to make the flip-flop metastableproof, the transition in the output value is delayed when the input value is in a metastable state. When the input value is no longer in the metastable state, then the transition in the output value is allowed to complete.