Abstract: A method and apparatus is disclosed for detecting edge-sensitive behavior from HDL descriptions of a circuit and inferring a hardware implementation of that behavior as a generalized edge-triggered D-type flip-flop with asynchronous set and clear inputs. The invention detects the edge-sensitive behavior from directed acyclic graphs (DAGS) that represent the individual signal nets of the circuit as affected by each process defined in the HDL description of the circuit. The invention then modifies each DAG to infer the asychronous control expressions and the data input expression necessary to control generalized flip-flop to emulate the behavior of the net represented by the DAG. The invention then creates a symbolic hardware implementation of the net's behavior using the D-type flip-flop and any combinational logic necessary to produced the inferred control signals.

Abstract: Disclosed is a semiconductor fuse structure having a low power programming threshold and anti-reverse engineering characteristics. The fuse structure includes a substrate having a field oxide region. A polysilicon strip that has an increased dopant concentration region lies over the field oxide region. The fuse structure further includes a silicided metallization layer having first and second regions lying over the polysilicon strip. The first region has a first thickness, and the second region has a second thickness that is less than the first thickness and is positioned substantially over the increased dopant concentration region of the polysilicon strip. Preferably, the first region of the silicided metallization layer has a first side and a second side located on opposite sides of the second region, and the resulting fuse structure is substantially rectangular in shape. Therefore, the semiconductor fuse structure can be programmed by breaking the second region.

Abstract: A method of plasma etching photoresist and sidewall polymer with an etch gas mixture comprising CF.sub.4 and H.sub.2 O demonstrating very aggressive ashrate of photoresist but maintains an exceptionally low etch rate for titanium nitride and other metals is provided. The very low TiN etch rate permits the inventive method to effectively breakdown sidewall polymer without removing any significant amount of these metals. The invention is particularly suited for stripping sidewall polymer from etched via holes and from etched metal lines.

Abstract: The present invention is directed to a method and apparatus for detecting edges through one or more opaque, planarized layers of material. Exemplary embodiments can take full advantage of decreased size geometries associated, such as 0.25 micron technologies, without suffering inaccuracies due to wafer misalignment during processing (e.g., during a photolithographic process). The invention is applicable to any process where an edge is to be detected through a planarized layer which is opaque to visible light. In an exemplary embodiment, an edge of an alignment mark can be detected using an energy source having a wavelength and angle of incidence specifically selected with respect to the optical characteristics and thickness of particular material layers being processed.

Abstract: A ball grid array (BGA) package configuration for packaging an integrated-circuit die includes a lead frame having a plurality of inwardly-extending bonding fingers and a centrally-located die-attach pad. The bonding fingers are disposed peripherally surrounding the die-attach pad. An integrated-circuit die is mounted on the die-attach pad. Bonding fingers are interconnected between the bonding pads on the integrated-circuit die and the plurality of bonding fingers. A plastic material is molded over the top of the lead frame and the die while still providing an exposed bottom surface of the bonding fingers on the lead frame. A solder mask is disposed over the bottom of the lead frame so as to form selective solder areas. Solder balls are attached to the selective solder areas.

Abstract: An architecture and method for communicating between multiple processors. In one embodiment, first data is transferred from a first processor into a first memory. In the present embodiment, multiplexing circuitry connects the first processor to the first and second memories, but the first processor only has access to the first memory. Similarly, second data is transferred from the second processor into the second memory. Multiplexing circuitry connects the second processor to the first and second memories, but the second processor only has access to the second memory. In the present embodiment, the multiplexing circuitry switches the connection between the first processor and the first and second memories and the second processor and the first and second memories. In so doing, the first processor is switched from having access only to the first memory to having access only to the second memory.

Abstract: The present invention is a desktop personal computer (PC) system having peripheral device bus mastering. The system has a Direct Memory Access (DMA) controller for transferring data to and from the memory of the desktop PC system. A hardware state machine is used for programming the DMA controller, generating and sending command signals, and receiving completion status after the transfer of data is complete. A bus controller is used for implementing a memory data transfer request from the DMA controller means and said hardware state machine means. A device controller, either a Universal Serial Bus (USB) controller or an Infrared Data Association (IrDA) controller, is used for receiving and responding to the command signals from the hardware state machine means, transferring data to and from the DMA controller means, and generating and returning a completion status to the hardware state machine means after the transfer of data is complete.

Abstract: A "wrapped-line" direct-mapped cache is disclosed that stores words with main-memory addresses that succeed a requested address where a conventional nonwrapped direct-mapped line-unit cache would store words with main-memory addresses that precede the requested memory address. Since succeeding addresses are more likely to be called "soon" after a requested address, the wrapped-line direct-mapped cache provides more efficient use of cache capacity, and thus more effectively enhances the performance of an incorporating system. The wrapped-line direct-mapped cache has indexed storage locations. Each storage location has sections for storing a tag, a string-boundary indicator, and a line of words. Each storage location has a line index, and each word position in a line has a word-position index. To determine whether a requested address results in a hit or a miss, the match logic divides the requested address into high, intermediate, and low segments.

Abstract: A system and method for determining which of plurality of peripheral components will have access to a peripheral component interconnect (PCI) bus when none of the plurality of peripheral components is currently requesting access to the PCI bus. In one embodiment a history buffer records all requests by a plurality of peripheral components for access to the PCI bus. The present invention then determines which of the plurality of peripheral components requests access to the PCI bus most often. Next, the present invention grants the peripheral component which requests access to the PCI bus most often access to the PCI bus when no other peripheral component is requesting access to the PCI bus. In so doing, the present invention "parks" the PCI bus on the peripheral component which has, in the past, requested access to the PCI bus most often.

Abstract: A system and method for preventing contention in a shared memory environment. In one embodiment, a first processor reads a traffic controller which is coupled to a shared memory and to a second processor. The first processor writes its identifier into the traffic controller provided that the traffic controller does not already have an identifier corresponding to the second processor stored therein. If the traffic controller does have an identifier corresponding to the second processor stored therein, the first processor periodically reads the traffic controller until the traffic controller does not have an identifier corresponding to the second processor stored therein. Once the traffic controller has the identifier corresponding to the first processor stored therein, the traffic controller allows the first processor to control access to the shared memory.

Abstract: A method is described for creating an inductor in the package for an integrated circuit. The inductor is formed by utilizing one or more of the bond leads as the core of the inductor and by winding a series of coils about the core in connection either with the bond pads of the integrated circuit itself or to other bond leads for connection outside the integrated circuit chip.

Abstract: A method and apparatus for designing circuits uses parameterized Hardware Description Language (HDL) modules stored in a library. A datapath synthesizer accesses the library and assigns values to parameters to form specific implementations of the parameterized HDL modules. The specific implementations of the parameterized HDL modules are used by the datapath synthesizer to implement an HDL circuit description.

Abstract: A computer system includes a central processing unit (CPU), system read-only memory (ROM), a random access memory (RAM) and a system controller. The system ROM includes a reset vector. A portion of the RAM is used to shadow the system ROM. The system controller is connected between the CPU, the system ROM and the RAM. The system memory includes an internal memory for storing first data. The system memory also includes logic which, in response to receiving an access to a reset vector stored in the system ROM, returns the first data stored in the internal memory.

Abstract: A clock signal is extracted from a received signal. An edge detector detects edges of the received signal, where the received signal transitions between a logic 0 and a logic 1. A center between each pair of consecutive edges is determined. Each center which is not within an associated correction window is discarded. An extracted clock signal is generated. The phase of the extracted clock signal is varied based on the centers between each pair of consecutive edges which are not discarded. In one embodiment, a current correction window size is varied based on whether an immediate previous center was within an immediate previous correction window. When the immediate previous center is discarded because it is not within the immediate previous correction window, the current correction window size is enlarged.

Abstract: The present invention is directed to a method and apparatus for accurately estimating signal delays of an electrical circuit by taking into account both resistance and capacitance of an interconnect network when determining both gate delays and interconnect delays of the circuit. Exemplary embodiments of the present invention, by providing a highly accurate estimate of signal delays, result in highly efficient, cost-effective electrical circuit design and fabrication. Further, a high degree of customer satisfaction can be realized because the possibility that a given electrical circuit will not comply with customer specified time constraints is minimal.

Abstract: Disclosed is a loadboard that includes a plurality of channel pins that are arranged on the loadboard. The plurality of channel pins are electrically routed on the loadboard to a receptacle that is configured to receive I/O pins of an integrated circuit chip. The loadboard further includes a programming and test circuit that is integrated on the loadboard, and is coupled to a set of the plurality of channel pins to enable communication with the integrated circuit chip. The programming and test circuit includes a programming sub-circuit for communicating a plurality of voltage levels set by a programming vector to the integrated circuit chip, and a bias sub-circuit for communicating a plurality of bias voltage levels set by the programming vector to the integrated circuit chip.

Abstract: A method for designing a constant multiplier system comprises identifying a repeated pattern in a minimal signed digit expression of a multiplier, designing a first accumulator stage to compute the product of a multiplicand by an instance of the pattern, and designing a second accumulator stage for accumulating shifted replicas of the pattern to yield a final product. Remainder terms, for example corresponding to non-zero digit positions not included in any instance of the pattern, are also accumulated at the second stage. By limiting the method to patterns with at least two non-zero values, the result tends to reduce the number of operations that must be performed to determine a final product. Thus, the size, complexity and speed of a constant multiplier system can be optimized.

Abstract: Disclosed is a method for making a high resistive structure in a salicided process. The method includes providing a substrate including at least one active device having diffusion regions and a polysilicon gate structure. Depositing a metallization layer over the substrate including at least one active device. Annealing the substrate to cause at least part of metallization layer to form a metallization silicided layer over the substrate that includes the at least one active device. Preferably, the metallization silicided layer lying over the diffusion regions and the polysilicon gate produces a substantially decreased level of sheet resistance. The method also includes forming a mask over the metallization silicided layer, and the mask being configured to leave a portion of the metallization silicided layer that overlies at least one active device exposed.

Abstract: A keyboard controller supports both a first keyboard/mouse interface and a second keyboard/mouse interface. Data is routed between the first keyboard/mouse interface and a first host interface when the first host interface is active. Data is routed between the first keyboard/mouse interface and a first shell when a second host interface is active. The first shell provides compatible connection between the first keyboard/mouse interface and the second host interface. Data is routed between the second keyboard/mouse interface and the second host interface when the second host interface is active. Data is routed between the second keyboard/mouse interface and a second shell when the first host interface is active. The second shell provides compatible connection between the second keyboard/mouse interface and the first host interface.

Abstract: A method for storing and transferring wave table audio samples from system memory to a cache unit. The method creates a linked-list of pages in system memory for storing the audio sample. The linked-list is actually a pointer list indicating the locations in system memory where the audio samples are stored. A Digital Signal Processor (DSP) is able to translate the starting address of the pointer list to retrieve a requested audio sample from the system memory. The requested audio sample is then transferred to the cache unit where the DSP is able to retrieve audio samples in a linear fashion at a rate much faster than individually fetching the required portions of the audio sample from the main memory of the system.