Abstract: A multi-cycle, non-parallel DES encryption scheme that supports CBC, OFB, CFB, and ECB modes of operation. Three independent cipher stages are coupled together in series in order to implement a high-speed DES core. Sixteen cipher operations are required for DES encryption and decryption. Hence, the data is routed through the DES core five times. On the sixth pass, the encrypted/decrypted data is taken from the output of the first cipher stage. This output can then be used to encrypt/decrypt any subsequent input data. A different key is supplied to each of the cipher stages for each cycle.

Abstract: A method for measuring alignment accuracy in a step and repeat system which includes projecting an array of rows and columns of grating features onto a wafer coated with a resist using a first stepping distance and using an increased exposure dosage from row to row of said array; projecting the same array over the first but using a different stepping distance along the rows and also a sufficient offset in the starting positions of the first and second exposures to form a phase difference between the two projection exposures which will result in a complementary alignment of the two exposures at least one column in the array.

Abstract: An arrangement for providing key switch actuation detection which reduces the number of key switch inputs required at a key switch controller. A key scanning system for detecting the activation of keys on a key-based input device is provided, having a plurality of logic level sensors to detect and temporarily store logic levels on corresponding connection nodes. A plurality of switches, each coupled to one of the keys, provides a pattern of logic levels on the connection nodes in response to the activation of a particular key. A logic monitor is coupled to the logic level sensors to detect the stored logic levels and recognize the activation of the particular key based on the pattern of the stored logic levels. A method for performing key switch actuation detection that reduces the number of required key switch inputs is also provided.

Abstract: A low voltage digital-to-analog converter (DAC) uses a resistor string to divide a supply voltage. The voltage output for the DAC is fixed at an intermediary node in the resistor string, and NMOS and PMOS transistors are used to switch in V.sub.SS and V.sub.DD respectively to nodes in the resistor string such that the NMOS and PMOS transistors are operated where they are most conductive. A decoder is used to decode the digital input to control the switches. One switch from each set of NMOS and PMOS transistors is activated for a given input, or thermometric decoding of the input is used to activate more than one switch from each set to preserve monotonicity. In an alternative embodiment, when matching of the resistors can be assumed, a two-step decoding process is used. An LSB decoder decodes the least significant bits of the digital input and controls how V.sub.DD is applied to a bank of LSB resistors through PMOS transistors, and how V.sub.

Abstract: A dynamic latching arrangement with a conditional driver, a system, and a method reduce power consumption, increase operating speed, and reduce the number of discrete components. The conditional driver selectively impresses a signal on an internal node of the circuit such that when a control signal is asserted, a signal related to the clock signal is generated, but when the control signal is not asserted, a different signal related to the clock signal is generated.

Abstract: An integrated circuit package of this invention includes a series of nonconductive rigid substrates, each substrate having a pattern of generally coplanar bond fingers embedded thereupon. An integrated circuit die is connected to individual bond fingers of varying bond finger patterns. Individual bond fingers are connected to package terminals by medial leads, which are generally perpendicular to the bond finger patterns. Semiconductor die packages having both top and bottom package terminals are thus produced. Methods and devices are shown.

Abstract: In a computer aided design system for assisting in the design and analysis of integrated circuits, users can specify an integrated circuit using either a conventional circuit component netlist, or an HDL circuit description. Timing constraints are specified using conventional system level timing constraints, at least one clock timing constraint and a plurality multi-cycle timing constraints specifying clock based timing constraints for the transmission of data between sequential data elements in which at least a subset of the clock based timing constraints concern timing constraints for duration longer than a single clock period. In addition, the user may provide the system with a plurality of constraint based timing path specifications, each indicating signal paths through the integrated circuit to which specified ones of the multi-cycle timing constraints are applicable and signal paths to which the specified ones of the multi-cycle timing constraints are not applicable.

Abstract: Encapsulated thermally enhanced (TE) and electrically and thermally enhanced (ETE) integrated circuit assemblies that include bulky thermally conductive heat sinks are disclosed. The integrated circuit assemblies are configured to prevent the formation of pinholes and IC package warpage without adding bulk or additional structures. The assemblies are repositioned, through an offset in the bonding fingers of the leadframe, so that the rates of mold flow in the two halves of the mold cavity are substantially balanced. The repositioning of the assemblies also substantially balances the amount of mold material in the mold halves, which prevents warpage in a finished IC package.

Abstract: A Mini-PCI (MPCI) interface, and associated circuits and methods are provided for connecting a Peripheral Component Interconnect (PCI) device to one or more external devices. The MPCI interface, circuits and methods provide for a substantial if not full implementation of a PCI Local Bus without requiring the standard number of pins, traces, or signals. The MPCI interface includes a PCI/MPCI bridge connected between a PCI bus and to up to eight external devices in the form of MPCI devices and linear memory devices. The PCI/MPCI bridge is capable of receiving an incoming PCI transaction and multiplexing some of its signals together to create a corresponding incoming MPCI transaction. This incoming MPCI transaction may then be passed over an MPCI bus, having fewer lines and optimally operating at a higher frequency, the external devices. The process is reversed for outgoing transactions, i.e., the MPCI transactions are de-multiplexed to create PCI transactions.

Abstract: A secure embedded memory management unit for a microprocessor is used for encrypted instruction and data transfer from an external memory. Physical security is obtained by embedding the direct memory access controller on the same chip with a microprocessor core, an internal memory, and an encryption/decryption logic. Data transfer to and from an external memory takes place between the external memory and the memory controller of the memory management unit. All firmware to and from the external memory is handled on a page-by-page basis. Since all of the processing takes place on buses internal to the chip, detection of clear unencrypted instructions and data is prevented.

Abstract: A reprogrammable state machine which allows the state flow and control outputs to be reprogrammed without requiring modification of the state machine. The reprogrammable state machine uses a reprogrammable logic unit to generate the state transitions and output transitions for each state of the reprogrammable state machine. A memory control unit is used to program the state machine reprogrammable logic unit with default settings for the state transitions and output transitions for each state of the reprogrammable state machine. The memory control unit is also used to reprogram the state machine reprogrammable logic unit with modified settings for the state transitions and output transitions for each state of the reprogrammable state machine which needs to be modified.

Abstract: A method for preventing oxygen microloading of an SOG layer. In one embodiment of the present invention, hydrogen is introduced into an etching environment. An etching step is then performed within the etching environment. During the etching step an SOG layer overlying a TEOS layer is etched until at least a portion of the underlying TEOS layer is exposed. The etching step continues and etches at least some of the exposed portion of the TEOS layer. During etching, the etched TEOS layer releases oxygen. The hydrogen present in the etching environment scavenges the released oxygen. As a result, the released oxygen does not microload the SOG layer. Thus, the etchback rate of the SOG layer is not significantly affected by the released oxygen, thereby allowing for controlled etchback of the SOG layer.

Abstract: An antifuse structure includes a first electrode, a layer of enhanced amorphous silicon over the first electrode, and a second electrode over the layer of enhanced amorphous silicon. The layer of enhanced amorphous silicon is formed by an ion-implantation of a neutral species and a dopant species into a deposited layer of amorphous silicon, such that the antifuse structure will have a stable conductive link in a programmed state and such that it will be less susceptible to off-state leakage in an unprogrammed state. A method for making an antifuse structure includes forming a lower electrode, depositing an amorphous silicon layer over the lower electrode, ion-implanting a neutral species and a dopant species into the amorphous silicon layer, and forming an upper electrode over the amorphous silicon layer.

Abstract: A universal asynchronous receiver/transmitter (UART) computer programming interface emulates three-wire interface control. A register select circuit is supplied with address signals from a host CPU and has a plurality of register outputs organized into first and second groups. One of these groups of outputs are those which are required for three-wire operation in communications devices; and these outputs are mapped to the appropriate communications devices or registers. The other group of outputs required for three-wire operation, but with no corresponding function in a communications device, are implemented by means of an UART emulator circuit producing a data output which is coupled to an internal data bus, along with the output of the registers for the communications devices.

Abstract: A circuit and method for providing VGA display data to a display of lower resolution, such as an LCD panel, is disclosed. The circuit detects a write to the Frame Buffer that stores the full resolution VGA image, determines the address within the Frame Buffer that was changed, then translates the Start Address of the circuit such that the recently updated data will be displayed at or near the center row of the display. The circuit blocks accesses to display data outside the range of data displayed on the lower resolution display such that the operation of the circuit is transparent to a conventional VGA controller, thereby providing automatic virtual display panning for VGA data that is displayed on a lower resolution display such as an LCD panel.

Abstract: In a computer implemented circuit simulator, a method is provided for measuring energy consumption of a circuit under test during a measurement interval. The method comprises a series of computer implemented steps. A supply voltage is applied to the circuit under test. A current flowing through the circuit under test is then measured. A mirror voltage, representative of the value of the current, is generated. A capacitor is charged, with a power parameter voltage equal to the product of the supply voltage and the mirror voltage, during the measurement interval. An accumulated voltage is measured across the capacitor, wherein the accumulated voltage is representative of energy consumed by the circuit under test.

Abstract: A circuit including a ferroelectric capacitor can be used to store the value of nodes of volatile logic elements in a logic circuit. In this manner, the state of a complex logic circuit, such as a CPU or an I/O device, can be stored in the non-volatile ferroelectric capacitors. After an accidental or planned power outage, the non-volatile ferroelectric capacitors can be used to restore the values of the nodes. Additionally, a planned power loss can be save system power in circuits that are power consumption sensitive.

Abstract: A computer system in which a host bus is relieved from the burdens of data transfers between main memory and devices connected to an input/output (I/O) bus. Instead, the invention operates to place most of the burden of the data transfer on an internal bus within a bus arbitration unit so that the host bus is freed up much sooner than conventionally achieved. As a result, the computer system has substantially better performance because the host bus is available for other processing operations instead of being tied up with data transfers with devices (e.g., peripheral devices) connected to the I/O bus.

Abstract: A method for enhancing sidewall polymer removal. In one embodiment of the present invention, O.sub.2 is introduced into an ashing environment at a flow rate of approximately 800 standard cubic centimeters per minute (SCCM). In the present embodiment, CF.sub.4 is also introduced into the ashing environment. The CF.sub.4 is introduced at a flow rate of approximately 80 SCCM. The ashing environment also has H.sub.2 O vapor introduced therein. In the present embodiment, the H.sub.2 O vapor is introduced into the ashing environment at a flow rate of approximately 80 SCCM. The ashing environment is used to selectively etch sidewall polymer material, thereby providing a method for removing sidewall polymer material without detrimentally etching other materials.

Abstract: A MOS transistor is fabricated by forming an inverse gate mask consisting of a lower silicon dioxide layer and an upper silicon nitride layer. The exposed channel region is thermally oxidized. The mask is removed to permit a source/drain implant. The oxide growth is removed so that the channel region is recessed. A differential oxide growth then serves to mask the source and the drain for channel threshold adjust and punch-through implants. A doped polysilicon gate is formed, with the thinner area of the differential oxide serving as the gate oxide. In the resulting structure, the punch-through dopant is spaced from the source and the drain, reducing parasitic capacitance and improving transistor switching speeds.