Abstract: A computer system having a multiplex address/data bus with a multiplex system controller and method therefor is disclosed which provides in a computer system having time shared use of a multiplex address/data bus to reduce the number of required pins for devices within the computer system, a CPU having at least one address bus, at least one data bus, at least one memory input/output, and at least one CPU control bus coupled thereto for sending and receiving information.

Abstract: A computer-aided method and system are provided for obtaining a measurement of the capacitance value of a device under test (DUT). The complex impedance of a device under test (DUT) is measured at two nearby frequencies using an RLC meter. The two complex impedance values are then stored in a computer readable medium. The DUT is modeled by a programmed computer as a four element RLC model circuit including a resistor and inductor in series with a parallel RC circuit having a single capacitor which represents the capacitance of the DUT. Four equations which describe the electrical characteristics of the four element RLC model circuit are stored in a computer readable medium. The four measured values of complex impedance are substituted by the computer into the four stored equations. Values are obtained for the four individual RLC circuit elements by solving the four equations. The four unknown values are obtained by use of an optimization routine and then stored to a computer readable medium.

Abstract: A method for substantially reducing variations in a programming voltage of an anti-fuse structure formed on an integrated circuit wafer. The anti-fuse structure has a metal-one layer, an anti-fuse layer disposed above the metal-one layer, a oxide layer disposed above the anti-fuse layer, and a via hole in the oxide layer through to the anti-fuse layer for receiving a deposition of a metal-two material. The method includes the step of rendering a selected anti-fuse area susceptible to fuse link formation by reducing a resistivity of the selected anti-fuse area to diffusion of atoms from one of the metal-one layer and the metal-two layer when a programming voltage is applied between the metal one layer and the metal two layer. The selected anti-fuse area is located in the anti-fuse layer and substantially adjacent to and outside of an anti-fuse area directly below the via hole. The method further includes the step of depositing the metal-two material into the via hole.

Abstract: An integrated circuit having a semiconductor substrate and an anti-fuse structure formed on the semiconductor substrate. The anti-fuse structure includes a metal-one layer and an anti-fuse layer disposed above the metal-one layer. The anti-fuse layer has a first resistance value when the anti-fuse structure is unprogrammed and a second resistance value lower than the first resistance value when the anti-fuse structure is programmed. There is further provided an etch stop layer disposed above the anti-fuse layer, and an inter-metal oxide layer disposed above the etch stop layer with the inter-metal oxide layer has a via formed therein. Additionally, there is further provided a metal-two layer disposed above the inter-metal oxide layer. In this structure, a portion of the metal-two layer is in electrical contact with the anti-fuse layer through the via in the inter-metal oxide layer.

Abstract: The present invention relates to a system and method for reducing the power consumption of a computer system, more specifically a notebook computer system. The system comprises a programmable frequency generator and a programmable power supply which alters the current operating frequency and voltage of the computer's microprocessor to match current operating conditions. If the microprocessor is not doing any meaningful work, the programmable frequency generator and the programmable power supply can reduce both the operating frequency and voltage thereby lowering the power consumption of the computer system based on the formula: power=voltage.sup.2 .times.frequency. It should be noted that the programmable frequency generator and the programmable power supply may be attached to other system components in the computer system that consume a large amount of the computer system's power.

Abstract: A digital positioning system for a joystick. The system uses a potentiometer having one input coupled to a constant supply voltage and a second input coupled to a joystick game port for generating a variable resistance representative of a current position of the joystick. A constant current source is coupled to the joystick game port for generating a current for converting the variable resistance representative of the current position of the joystick to a voltage level representative of the current position of the joystick. An analog-to-digital (A/D) converter circuit is coupled to the joystick game port and is used to convert the voltage level representative of the current position of the joystick to a digital representation of the current position of the joystick.

Abstract: A phase locked loop including a comparator, a VCO controller, and a VCO having a multi-stage oscillator portion and a combinational logic portion. The comparator is responsive to an input clock and a VCO comparison clock and is operative to produce a comparator output signal. The VCO controller is responsive to the comparator output signal and is operative to produce a VCO control signal. The multi-stage oscillator portion is configured to oscillate at a VCO clock frequency during a steady state condition under the control of the VCO control signal, and is further operative to develop a plurality of clock phases at the VCO clock frequency. The combinational logic portion is responsive to at least some of the plurality of clock phases and is operative to combine clock phases to create an output clock having an output clock frequency that is a multiple of the input clock frequency.

Abstract: The present invention relates to a method and device for providing CMOS logic which can be operated at various operating voltages, without resulting in unbalanced operation of n-channel and p-channel CMOS transistors. In accordance with the present invention, CMOS circuitry can be provided that is operable over a range of voltages (e.g., a range from below 3 volts to a range over 5 volts) without producing unbalanced operation of n-channel and p-channel transistors. Thus, integrated circuits formed in accordance with the present invention can be operated at different voltage power sources without requiring a redesign or relayout of the integrated circuit. In accordance with the present invention, CMOS transistors can be fabricated without increased fabrication complexity to provide transistors which operate within a relatively safe region of their operating characteristics and which operate with a speed that is unaffected by the reduced voltage supply (i.e.

Abstract: A method of forming sharp oxide peaks on the surface of a semiconductor wafer for the purpose of conditioning polishing pads used during a Chemical Mechanical Polishing process is disclosed. In order to create oxide peaks on the surface of a wafer, additional elements are added to a trace layer of the wafer. An oxide layer is deposited over the additional elements using an Electron Cyclotron Resonance Chemical Vapor Deposition process, which includes a sputtering step, in order to create sharp peaks in the oxide layer over the additional lines. In some embodiments, the additional elements may be formed from a multiplicity of rectangular blocks over which pyramid-like oxide peaks are created. In others, they may be formed from a multiplicity of rectangular blocks connected by narrow lines over which pyramid-like oxide peaks and knife-edged peaks, respectively, are created.

Abstract: A digital power management system for an analog-to-digital converter operates to cause the sample rate of the analog-to-digital converter to function at an original desired frequency so long as changing input signals are present. Whenever activity at the input of the analog-to-digital converter ceases to change, the system automatically decreases the clock signal sampling rate to a slower clock frequency, or shuts down the application of clock signals. This conserves power until a change in the analog input is detected, whereupon the system automatically increases the sample clock frequency back to the original frequency.

Abstract: An antifuse structure includes a first electrode, a layer of enhanced amorphous silicon over the first electrode, and a second electrode over the layer of enhanced amorphous silicon. The layer of enhanced amorphous silicon is formed by an ion-implantation of a neutral species and a dopant species into a deposited layer of amorphous silicon, such that the antifuse structure will have a stable conductive link in a programmed state and such that it will be less susceptible to off-state leakage in an unprogrammed state. A method for making an antifuse structure includes forming a lower electrode, depositing an amorphous silicon layer over the lower electrode, ion-implanting a neutral species and a dopant species into the amorphous silicon layer, and forming an upper electrode over the amorphous silicon layer.

Abstract: A system and method for emulating the state of a soft reset within a processor device without requiring a dedicated soft reset external pin associated with said processor device. The novel system includes control circuitry coupled to a processor device for detecting a number of conditions used to cause the processor device to execute a soft reset. In processor devices that contain a write-back cache, the soft reset signal resets the configuration of the processor device and returns the processor to "real-address mode" addressing, but does not destroy the contents of the write-back cache (unlike a regular reset). Upon detecting a soft reset attempt, the novel system generates a System Management Interrupt (SMI) which is responded to by an interrupt handling routine also of the novel system. This interrupt handling routine contains a set of configuration data (stored in memory) that represents the expected state of the processor device after a soft reset.

Abstract: A key handling circuit for a switching matrix having row and column conductors includes bidirectional drives for the row conductors and the column conductors. The row drive and the column drive are in a low conductive condition except when a relevant key switch is activated. The row drive provides a current input for the column drive in one phase of operation and the column drive provides a current input for a row drive in a second phase of operation.

Abstract: This is an improved FIFO controller which is capable of buffering data between systems which are asynchronous relative to one another and is free of false flags and internal metastability. The FIFO controller comprises a controller means for receiving read/write data strobes and for generating an initial read/write pointer and a next read/write pointer. Memory means are coupled to the controller means for storing the read/write pointer and read/write data information. Flag generation means are coupled to the controller means for computing a status of the FIFO flags and for preventing momentary false flags.

Abstract: A method is described for reducing light scatter in lithographically producing a resist feature wherein the dosage of light beyond the immediate periphery of the desired feature is subjected to a lower dosage of light than is required to properly define the edges of the resist feature. In addition, a mask is described which is partially opaque in those areas remote from the area delineating the desired feature.

Abstract: A method for fabricating a semiconductor integrated circuit structure having a reduced width gate electrode. A pre-gate electrode having a width is first delineated by conventional lithography techniques. The conductive layer is partially etched to expose a first and second pre-gate side wall. With the pre-gate side walls exposed, the structure is oxidized to grow an oxide layer on the pre-gate side walls, thereby consuming a predetermined amount of the conductive material. The newly formed oxide layer is then removed to reduce the pre-gate width while retaining at least a portion of an oxide layer above the conductive layer as a mask. The reduced width gate electrode is completed by etching the remaining unmasked conductive layer.

Abstract: The present invention relates to a system and method for implementing peripheral device bus mastering in a mobile computer system. The system uses the mobile computer system's microcontroller for programming a DMA controller, generating and sending command signals, and receiving completion status after transfer of data is complete. The micro-controller accesses a data buffer descriptor list. The data buffer descriptor list describes each data transfer that the micro-controller initiates, controls, and completes. The Direct Memory Access controller which is programmed by the micro-controller transfers data to and from a memory section of the mobile computer system. A bus controller is used for implementing a memory data transfer request from the DMA controller means and the micro-controller means.

Abstract: A processing system and method is disclosed to access non-contiguous memory locations within a memory block. An address is generated that has a first group of bits and a second group of bits. The first group is decoded to select one of a number of memory blocks. The second group has n bits configured to select any one of (2.sup.n -(n+1)) unique combinations of the locations within the selected block. This second group provides a different pattern corresponding to each different combination of the locations within the selected block. An application of this addressing scheme for video graphics processing is also disclosed.

Abstract: The method implements implicit sequential behavior using a general finite state machine architecture (FSM) through the systematic evaluation of control flow graphs (CFGs) having one or more weight statements which are sensitive to the same unique clock edge. Each of the weight statements contained in the CFG are assigned a state in the state machine. All of the executable paths between each weight statement are fully evaluated on a node-by-node basis. From this evaluation process, expressions are extracted which define combinational logic necessary to produce additional inputs to the FSM to produce the next state, as well as expressions representing outputs of the FSM as associated with each transition from one state to another. The method also deals with proper evaluation of unrollable loops.

Abstract: The present invention is a system and method for implementing peripheral device bus mastering in a mobile computer system. The system uses the micro-controller of the mobile computer system to program a DMA controller. The DMA controller transfers data to and from the memory of the mobile computer system. A bus controller which is coupled to both the micro-controller and the DMA controller implements a memory data transfer request from the DMA controller and the micro-controller. A device controller, either a IDE hard disk controller or an ECP parallel port controller, is also coupled to the DMA controller and the micro-controller. The device controller receives and responds to the command signals from the micro-controller by transferring data to and from the DMA controller means and generating a completion signal when the transfer is complete.