Abstract: A multi-mode infrared interface allows for the selection of an encoding mode from a plurality of modes for infrared light transmission. When there is a transmission, an outgoing serial data stream is produced. The infrared interface transmits the serial data stream by infrared light using the selected mode. For example, a first mode is serial data stream transmission where an IR light pulse is transmitted for each bit of data having a first value. A second mode is modulated serial data stream transmission where a modulated IR light pulse is transmitted for each bit of data having a first value. A third mode is REDEYE transmission using the HP Redeye "REDEYE" format. A fourth mode uses a format defined by a user in software.

Abstract: A conductive via structure establishes an electrical interconnection between two conductive layers in a semiconductor structure by connecting a first conductive layer on a semiconductor substrate to a second conductive layer by means of a conductive via structure extending through a non-conductive layer separating the two conductive layers. The non-conductive layer preferably includes a layer of spin-on-glass (SOG), and is provided with a via aperture therethrough. A conductive spacer, preferably of TiW, is fabricated within the via aperture in abutment with the walls of the via aperture. A second conductive layer is fabricated over the non-conductive layer, the conductive spacer, and within the via aperture, to establish the completed electrical interconnection. The via structure reduces out-gassing and chipping from the SOG layer, yet provides a low electrical resistance path between the two conductive layers.

Abstract: A thermal management device for controlling the temperature of a computer processor chip, by controlling the operating speed of the processor, including a temperature sensitive circuitry incorporated within a packaged clock chip for connection to a processor. A thermal management method for controlling the temperature of a computer processor chip includes sensing a temperature with a temperature dependent circuitry integrally formed in a packaged clock chip, in which the sensed temperature is a function of the temperature of the computer processor chip, generating a clock control signal with the temperature dependent circuitry and sending the clock control signal to a clock generator also integrally formed in the clock chip, and sending a clock signal from the clock generator to the computer processor chip in order to control the operating frequency, and thus the temperature, of the processor.

Abstract: A resistor formed in a well adjacent to a transistor serves as a ballast resistor for the transistor. The transistor is formed in a first region on a substrate. The first region is of a first conductivity type. A well of second conductivity type is formed adjacent to the first region. A gate region is formed over a portion of the first region. Concurrently, a covering is formed over a first area of the well. The covering and the gate region are comprised of the same material. Source/drain regions of the second conductivity type are formed on either side of the gate region. The source/drain regions are of the first conductivity type. A first source/drain region extends into the well. Concurrent to the forming of the source drain regions, a doped region is formed within the well. The doped region and the first source/drain region have the same doping density. The doped region is physically separated from the first source/drain region by the first area of the well.

Abstract: A joystick system provides a digital representation of the setting of a joystick potentiometer. The voltage of the joystick is supplied to an analog-to-digital converter, the output of which then is used to load a counter. In one mode of operation, the counter counts down to zero at some multiple of the sample rate. When the counter reaches zero, the time interval representative of the joystick position is indicated; and this output is indicative of the joystick position. In an alternative mode of operation, the counter is used as a data latch and the joystick position is digitally read from the counter, which keeps the data latched until the next sample cycle from the joystick position.

Abstract: A leadframe ball grid array package for packaging an integrated-circuit die includes a metallic substrate having a central portion and a leadflame having a plurality of inwardly-extending bonding fingers and a centrally-located open portion. The leadframe is directly attached to the metallic substrate by a non-conductive adhesive so that the open portion thereof overlies the central recessed portion of the metallic substrate. An integrated-circuit die is mounted in the central portion of the metallic substrate. The bonding fingers are disposed peripherally surrounding the integrated-circuit die. Bonding wires are interconnected between bonding pads formed on the integrated-circuit die and the plurality of bonding fingers. A solder mask is disposed over the top surface of the leadframe so as to form selective solderable areas. Solder balls are attached to the selective solderable areas. A plastic material or a lid is applied over the top surface of the die, bonding fingers and bonding wires.

Abstract: A hybrid Harvard/Von Neumann data processing system utilizes a Harvard architecture processor with a combined data/instruction memory. A dual-port random-access instruction buffer between memory and the processor provides much of the performance enhancement of an instruction cache when used with a RISC instruction set, but at a much lower cost. The resulting system serves as an entry-level computer system of a series of compatible computers, led at the high end by a Harvard processor with full data and instruction caches.

Abstract: A method of fabricating an integrated circuit on a silicon substrate in such a manner as to avoid the requirement of over-etching the polysilicon usually necessary to prevent shorting of adjacent devices by poly filaments caused by deep polysilicon pockets in notch areas created in the field oxide during its growth. The notches are prevented by forming the nitride mask with sloped rather than perpendicular side walls. The sloped side walls present less resistance to the growing oxide than does the usual perpendicular wall and thus does not dig into the growing oxide to form the notches. The edge of the resultant field oxide is therefore smoother, permitting easier and more complete removal of the polysilicon without the need for over-etching.

Abstract: A method of forming a metal interconnect structure for a CMOS integrated circuit provides for deposition of via metal prior to formation of an intermetal dielectric. After a submetal dielectric is deposited, lower metal and via metals are deposited. Gradient photolithography is used to define a via pattern and a lower metal pattern in a positive photoresist. After etching, the lower metal assumes the lower metal pattern and the via metal assumes the via pattern. A three-layer intermetal dielectric includes a spin-on glass sandwiched between two deposited silicon dioxide layers. The resulting structure is polished until at least some of the vias are exposed. Other vias can be exposed by via apertures that are define photolithographically. An upper metal layer is then deposited, filling the via apertures. The upper metal is then patterned to complete the interconnect structure. This method provides that via metal is insulated from spin-on glass moisture by the deposited oxide.

Abstract: An improved method for transferring a semiconductor carrier tray is disclosed. The method herein provides for transferring a semiconductor carrier tray from a first location to a second location by first positioning a cap member to cover the mouth of at least one cup of a semiconductor carrier tray. The capping member contacts the uppermost surface of the cup wall. A partial vacuum is applied to the capped cup, and atmosphere is evacuated from the capped cup, adhering the semiconductor tray to the capping member. Movement of the capping member causes movement of the carrier tray from a first location to a second location. When the carrier tray has been positioned at its final destination, the vacuum is released causing separation of the carrier tray and the capping member. A vacuum cap apparatus is also disclosed.

Abstract: A system and method for reducing the contact resistance associated with tungsten plug contacts to P-doped diffusion regions of a semiconductor device. Before or during the formation of the tungsten plug contacts, a high energy, low dosage of an N-dopant or neutral species such as silicon or germanium is implanted into the P-doped diffusion regions of the semiconductor device. The implantation causes lattice damage within the P-doped diffusion regions, enhancing diffusion of the P-dopant within the P-doped diffusion regions. This results in the P-dopant diffusing toward the contact, replacing dopant lost to segregation into the contact metalization, and thus reducing the contact resistance.

Abstract: A computer system is disclosed that permits multiple write buffer read-arounds. The system comprises a CPU (Central Processing Unit) for executing cycles for the computer system, a cache coupled to the CPU for storing data, a write buffer coupled to the CPU for receiving write data from the CPU, an arbiter to control bus accesses to the slave, and processing signals coupled between the cache and the write buffer for permitting the CPU to read-around the write buffer a plurality of times before the write data in the write buffer is flushed therefrom. The processing signals determine when the data stored in the write buffer is also stored in the cache, and, therefore, the cache is permitted to read-around the write buffer more than one time as long as the write buffer has the same data stored therein as exists in the cache.

Abstract: A hardware timing system for a cellular telephone comprises a master counter and a slave counter. The slave counter controls timing window generators in synchronism with the time frame of the local base station. The phases of timing frames of other base stations are monitored using the master counter.

Abstract: A power usage simulator and method for generating a baseline power usage model for a representative sample of cells in a circuit cell library, where the baseline power model is based on signal slew rates and output load for a given of environmental conditions. The baseline power usage model is aggregated for a representative set of library cells so as to provide an accurate baseline power usage computation for all logic cells rather than for each transistor or each individual cell. Thereafter, power coefficient sensitivities to varying temperature, supply voltage and process conditions are determined for each power coefficient. Power coefficient sensitivities are measured by comparing the ratios of the measured power coefficients resulting from maintaining two of the three parameters (temperature, voltage and process) at baseline values while varying the third parameter over its entire range.

Abstract: A computer-aided design method and apparatus for compacting semiconductor circuit layouts to meet a specified set of design rules begins by fracturing a specified circuit layout into a set of trapezoids and storing the resulting cells in a database identifying the boundaries of each cell, and the cell adjacent each boundary. The method additionally includes a procedure for minimizing wire lengths in the compacted layout. Nonempty cells are identified as being of specific materials, and empty spaces between cells are represented. For each cell boundary, the database also stores data representing the boundary edge's end points. Neighboring cells on the same and related layers of the circuit layout share edges in the database. When a point on an edge of a cell is moved, the edge of each neighboring cell that shares that point is also moved. To adjust a circuit layout, the cells in the layout are processed in a sorted order.

Abstract: The present invention relates to a universal contactor system for testing multiple size BGA devices on multiple types of testing equipment. The universal contactor system is comprised of a plurality of pogo pin which provide a connection between the BGA device to be tested and a DUT (Device Under Test) board. A contactor block having a plurality of apertures therethrough is used for holding the plurality of pogo pins. A guide plate having a center opening is coupled to the contactor block. The center opening in the guide plate is used for aligning the BGA device to be tested on the contactor block. The guide plate may be replaced with guide plates having a larger or smaller opening to align BGA devices of a larger or smaller size on the contactor block.

Abstract: A package for an integrated-circuit includes a package body having a die-cavity formed therein. A die-attach pad is formed in the package body adjacent the die-cavity. An opening is formed in the central portion of the die-attach pad for exposing one side of the integrated-circuit die so that an external cooling media can directly contact the exposed side of the integrated-circuit die. The die-attach pad can be formed as a die-mounting ring adjacent the die-attach cavity. The peripheral edge of the integrated-circuit die is fixed to a mounting surface on the die-mounting ring portion to accommodate direct cooling of the exposed side of the integrated-circuit die. The mounting surface of the die-mounting ring extends beyond the peripheral edge of the integrated-circuit die to accommodate a range of sizes of the integrated-circuit die.

Abstract: A multi-layer substrate structure and a method for fabricating the same are provided. Thin metal foils are laminated on the top and bottom sides of a non-conductive layer so as to form a laminated substrate. A plurality of plated-through holes are formed in the laminated substrate and are then filled with an epoxy. The laminated substrate is then patterned and etched. Epoxy layers are disposed on both sides of the laminated substrate. The laminated substrate is formed with a plurality of smaller plated-through holes extending through the epoxy layers and with a cavity to receive an integrated-circuit die. The through holes and the epoxy layers are metallized on both sides of the laminated substrate. The laminated substrate is patterned and etched again. A solder mask is applied on both sides of the laminated substrate so as to form selective wire bondable areas and selective solderable areas. The integrated circuit die is disposed in the center of the cavity and has a plurality of bonding pads.

Abstract: A method for forming a scribe line on a semiconductor wafer including the steps of: (a) providing a semiconductor substrate; and (b) sequentially providing a plurality of layers over the semiconductor substrate of alternating conductive and insulating types, where each of the layers is provided with an elongated opening is formed relative to a desired scribe line position, and where the openings of at least some of the plurality of layers are wider than openings of preceding layers such that at least one sidewall of a completed scribe line has a pronounced slope extending outwardly from its base. The structure of the present invention is, therefore, a scribe line having sloped sidewalls that greatly reduces scribe line contamination problems and enhances planarization during subsequent spin-on-material processes. The scribe lines can either be elongated openings in the layers, or an elongated mesa formed in the layers.

Abstract: A method for designing a circuit layout which includes the steps of supplying a predictive capacitance value for at least one net of a circuit layout, and placing and routing all nets of the circuit layout using at least one predictive capacitance value as a layout design constraint.