Abstract: A method for making an integrated circuit characterized by: determining a range of bonding pad pitches which varies between a minimum bonding pad pitch and a maximum bonding pad pitch; setting a driver pitch to the minimum bonding pad pitch; forming a base set including a plurality of drivers having the determined driver pitch; forming customization layers over the base set, where the customization layers include a plurality of bonding pads having a pad pitch greater than the minimum bonding pad pitch but less than or equal to the maximum bonding pad pitch; and coupling some, but not all, of the drivers to the pads. As a result, a single base set can be used to make integrated circuits having a range of bonding pad pitches. The method and structure of the present invention are very well adapted for use in gate array integrated circuits.

Abstract: The present invention relates to a system and method for passing Industry Standard Architecture (ISA) legacy interrupts across Peripheral Component Interconnect (PCI) connectors. The system interconnects a plurality of PCI devices coupled to a PCI bus such that a last interrupt pin of each of the plurality of PCI devices are coupled together in a directly bussed manner to provide a serial interrupt signal line. The remainder of the interrupt pins of each of the plurality of PCI devices are coupled together in a barber pole manner.

Abstract: A system for testing a digital counter of mn stages, in which the counter is organized into m segments, each of n bits, includes a two input exclusive OR gate connected between each of the m segments. One of the two inputs of each exclusive OR gate is obtained from the carry output of a lower order one of the m segments, and the output of each exclusive OR gate is connected to the carry input of the next higher order one of the m segments. The other inputs to the exclusive OR gates are obtained from a test signal enable input, which is driven high (binary "1") for the test mode of operation. The counter is fully exercised in the test mode in a parallel operation, with full testing of the carry bits from one segment to the next, without any interruption in the clock signal input stream.

Abstract: A method and system are designed to guarantee availability of ownership of an ISA bus by a bus mastering or a direct memory access device in a system also including a PCI bus. This is accomplished by placing a lock on the PCI bus through a bridge device to a configuration read of a PCI configuration space register. Once the lock is established, other PCI devices are prevented from locking any other resource on the PCI bus. The PCI configuration space exists outside of the memory or I/O ranges to which an ISA resident device can generate access. Consequently, whenever the ISA resident device generates its access, it is to a device known not to be in a locked state. Consequently, the bus transaction is capable of completion within the time limit expected by the ISA resident device.

Abstract: A link system controller is interposed between a PCI bus and the CPU data bus and memory data bus of a personal computer system to ensure that the transfer of data from the PCI bus to the CPU data bus occurs on different clock signals from the transfer of data from the PCI bus to the memory data bus. This is accomplished by an authorizing circuit, which alternately enables a CPU bus interface controller and a memory data bus controller in response to alternating clock signals. This prevents simultaneous switching of the devices on both the CPU data bus and the memory data bus, to reduce the generation of noise below an acceptable threshold; so that the operation of the IC system device is not impaired.

Abstract: An integrated circuit package of this invention includes a series of nonconductive rigid substrates, each substrate having a pattern of generally coplanar bond fingers embedded thereupon. An integrated circuit die is connected to individual bond fingers of varying bond finger patterns. Individual bond fingers are connected to package terminals by medial leads, which are generally perpendicular to the bond finger patterns. Semiconductor die packages having both top and bottom package terminals are thus produced. Methods and devices are shown.

Abstract: An interrupt based positioning system for a joystick. A potentiometer is coupled to the joystick for supplying a voltage signal representative of a current position of the joystick. An analog-to-digital converter changes the voltage signal to a digital voltage signal which is then stored in a register. Interrupt generation logic monitors the output of the register and generates a position interrupt signal when the digital voltage signal stored in the register indicates a change in the axial position of the joystick.

Abstract: A link system controller is interposed between a PCI bus and the data bus and memory data bus of a personal computer system to normally allow transfer of write information from the PCI bus to DRAM memories on the memory data bus. Whenever a request is made for the transfer of data to the CPU data bus, a CPU bus interface controller requests release of the system from the DRAM controller. The DRAM controller then grants permission or releases control to the CPU bus interface whenever the DRAM controller is not writing data out to the DRAM data bus. When this release is effected, the transfer of write data to the memory data bus is prevented and transfer of data to the CPU data bus is enabled. This prevents simultaneous switching of the devices on both the CPU data bus and the memory data bus, to reduce the generation of noise; so that the operation of the IC system device is not impaired.

Abstract: Forming tungsten plugs allows for a conformal step coverage into contacts in semiconductor wafer processing. By rinsing the wafers after the tungsten etchback but before the wafers have a chance to enter an oxygen-containing environment, the amount of fluorine-containing residue removed from the wafer can be increased. In this way, the connection between the tungsten plugs and a metallization layer can be improved.

Abstract: A purge process for an LPCVD TEOS silicon dioxide deposition method uses a series of five purge cycles to allow low-defect wafer processing with less frequent chamber removal and cleaning. The purge process begins by loading dummy wafers into the chamber. Chamber pressure is reduced to below 20 mTorr. A maximal nonreactant gas flow for two minutes is used to dislodge and carry away contaminants such as flakes from silicon dioxide previously deposited on the chamber wall. After the first four of five purge cycles, the method returns to the reduction of chamber pressure, e.g., by maintaining the vacuum on while the gas sources are turned off. After the fifth cycle, the chamber is slowly filled with nitrogen until ambient pressure is reached. Then the dummy wafers are removed. The system is then ready for processing product wafers with reduced particle counts. The purge process is benign in that it only uses equipment and procedures of the type used during product wafer processing.

Abstract: A method and apparatus for characterizing the timing behavior of datapath in integrated circuit design and fabrication. A set of circuit specifications for an integrated circuit are developed and described in a hardware description language (HDL) description. A datapath library including datapath cells and a gate library including primitive gate cells are provided, and a netlist is synthesized from the HDL description. The netlist is composed of datapath cells from the datapath library and primitive gate cells from the gate library. If a datapath cell instance in the netlist does not meet the timing constraints imposed by a user for the circuit, an alternative datapath cell instance can be substituted for that cell instance in a resynthesis and optimization step. An integrated circuit is preferably fabricated as specified by the resynthesized netlist. The netlist is preferably resynthesized multiple times in an iterative loop to optimize the netlist according to the constraints.

Abstract: Signalling apparatus are used for monitoring a clock signal from a system controller to a processor. If the clock signal is low, indicating that the processor is disabled, the signalling apparatus will place the cache memory in a "sleep" mode. Thus, the signalling apparatus allow a computer system, upon which the signalling apparatus is a part of, to lower its power consumption. If the computer system is a portable computer system, the signalling apparatus will lower power consumption thereby extending the lifetime of the portable computer's batteries.

Abstract: Disclosed is an apparatus and method for manufacturing antifuse structures on topographically varying silicon substrates. The antifuse structures are intelligently formed over topographically lower silicon substrate regions such that subsequent via hole etching processes do not over-etch underlying antifuse structures. Also discloses an apparatus and method for designing dummy metallization and polysilicon features in close proximity to antifuse structures such that subsequently deposited dielectric materials are induced to form thicker dielectric layers over antifuse structures. Advantageously, subsequent via hole etching does not substantially remove antifuse structure materials with may cause detrimental ionic contamination or antifuse infant mortality. In this manner, standard via hole etching techniques may be implemented for all inter-layer via holes without concern the concern of over-etching sensitive underlying devices.

Abstract: The present invention relates to a system and method which has automatic enabling and disabling capabilities for prefetching and transferring sequentially located data from system memory to a First In First Out (FIFO) queue. When a Peripheral Component Interconnect (PCI) initiator signals for a data read, a minimum unit of data will be transferred from system memory to the FIFO queue. Only after seeing a certain number of consecutive data read requests from the same PCI initiator will the system begin to sequentially prefetch data from system memory and to transfer the prefetched data to the FIFO queue.

Abstract: A comparator used in an enhanced N-WELL pad voltage tracking circuit for high (5 Volts) voltage-tolerant buffers is designed to eliminate current leakage when the input/output is tristated and is being driven externally by a weak voltage source. This is accomplished by comparing the pad voltage supplied from the external source to a reference voltage that is a predetermined amount (VTP) less than the low internal voltage source (VDD). Thus, switchover for tracking of the N-WELL voltage tracks very closely the voltage VDD, reducing the differential voltage between the N-WELL and the pad on the pull-up driver for the system, thereby keeping the driver off and eliminating leakage current. The reference voltage is generated either by a diode voltage drop or by a weak source follower.

Abstract: An input buffer for a CMOS integrated circuit comprises parallel pairs of complementary PMOS pull-up and NMOS pull-down transistors. For each NMOS transistor, a polysilicon NMOS gate lead structure includes three sections: a heavily doped gate section, an undoped resistor section, and a heavily doped contact section. The heavily doped contact section is contacted by a metal delivering a logic low voltage (V.sub.SS) so that the NMOS gate is resistively coupled to V.sub.SS. This resistance cooperates with the gate to drain resistance to define a voltage divider between V.sub.SS and V.sub.IN. This voltage divider leaves the gate at a small positive voltage during an electrostatic discharge event. This ensures that all NMOS transistors of a buffer become current bearing before any of them enters second breakdown. This arrangement maximizes input-buffer protection from electrostatic discharge events. The novel NMOS arrangement is readily compatible with CMOS fabrication techniques.

Abstract: A fully associative cache memory has a finite state machine which creates and maintains a linked list structure within the cache. This linked list structure allows the fully associative cache memory to be implemented in a structure other than a complex FIFO arrangement, as is typically required by systems of the prior art.

Abstract: An improved bus architecture is provided in which the bus connects a single master to multiple targets including one primary target. Bus usage is predominately between the master and one primary target at a very high data transfer rate. Traffic between the master and other secondary targets has a much lower bandwidth requirement. The bus uses a single frequency clock for transfers involving the primary target and transfers involving the secondary targets. In accordance with one embodiment of the invention, the master is connected to the primary high bandwidth target using a high speed protocol and separate read and write data paths which are always driven (i.e., never tri-stated). Always driving the high speed data paths avoids the increased area and decreased performance that would be entailed by adding additional gating. The lower bandwidth targets are supported on a single bi-directional data path to minimize area.

Abstract: A structure is used for electrostatic discharge protection of an integrated circuit. The modified ladder structure includes drain regions which extend from an output pad. These are interleaved with source regions. For example, for a structure with two drain regions and two source regions, a first drain region extending from the output pad is separated from a first source region by a first gate region. A second drain region extending from the output pad is separated from the first drain region by a first insulating region. A second source region is separated from the second drain region by a second gate structure. For a structure with four drain regions and three source regions, there is additionally, a third drain region extending from the output pad. The third drain region is separated from the second source region by a third gate region. A fourth drain region extending from the output pad is separated from the third drain region by a second insulating region.

Abstract: An event driven power management control system. The event driven power management control system is compatible with existing CPU power management control units which only monitor CPU activity. The event driven power management control system is able to modify a STPCLK# signal asserted by the CPU power management control unit if external or internal events in the computer system require the CPU to run at full speed in order to service the break event.