Abstract: A method for forming a scribe line on a semiconductor wafer including the steps of: (a) providing a semiconductor substrate; and (b) sequentially providing a plurality of layers over the semiconductor substrate of alternating conductive and insulating types, where each of the layers is provided with an elongated opening is formed relative to a desired scribe line position, and where the openings of at least some of the plurality of layers are wider than openings of preceding layers such that at least one sidewall of a completed scribe line has a pronounced slope extending outwardly from its base. The structure of the present invention is, therefore, a scribe line having sloped sidewalls that greatly reduces scribe line contamination problems and enhances planarization during subsequent spin-on-material processes. The scribe lines can either be elongated openings in the layers, or an elongated mesa formed in the layers.

Abstract: A CMOS small-signal amplifier is arranged to drive separately but in synchronism the transistors of an output stage comprising a first output transistor of a first conductivity type and a second output transistor of a second conductivity type. Each of these output transistors is driven by a respective intermediate stage comprising a current source transistor and a driver transistor directly coupled to an input terminal and a control node of the respective output transistor. The current source transistors are biassed such that the said output transistors have a symmetrical duty cycle. There may be a single bias line connected to a current source transistor in one intermediate stage and a system of current mirrors coupling the bias line to the current source transistor in the other intermediate stage.

Abstract: The present invention is directed to a system and methodology where virtually no DC power dissipation is used during keyboard scanning or key closure. This is done by replacing the passive pull-up (or pull down) resistors of previous schemes by input/output (I/O) circuits with repeaters and utilizing a scanning protocol and methodology which take advantage of the bidirectional I/O devices with repeaters. In a preferred embodiment, a plurality of CMOS bidirectional I/O circuits with repeaters are used, one for each row and column line in a switch matrix. A low power, switch activation scanner circuit determines activation of a switch. The circuit is coupled to or may include a plurality of switches, arranged in rows and columns, each row output line intersecting each column output line at a different node, for coupling a first row to a first column at a first node when a first switch of the plurality of switches is activated.

Abstract: A hardware graphics accelerator (HGA) system which has a source memory element which is loaded to initiate HGA operations operates in two modes: (1) a FIFO mode for normal HGA operations and (2) a recirculate mode for high speed pattern transfers and pattern expands by the HGA. The use of the second mode simplifies the structure and increases the operating speed of the HGA and its associated CPU by eliminating the use of the dedicated pattern registers and pattern control multiplexers of prior art HGA systems.

Abstract: A universal semiconductor interconnect test structure and method for using the test structure is provided for detecting the presence of electrical open or short circuits within the test package. In one embodiment, the test structure comprises a layer of electrically non-conductive substrate and a bonding layer of electrically conductive material over the substrate layer. In a second embodiment, the universal test die comprises a layer of electrically non-conductive substrate and a pattern of electrically conductive material over the substrate layer, wherein the pattern forms a continuous array of individual bonding areas, each of the bonding areas being electrically isolated from adjacent bonding areas by a gap, and wherein the effective pitch of the bonding areas is not more than 25 microns. The universal test die of the present invention is suitable for developing wire bond and mold processes for all pad pitches, all pad layout designs, all package types, and all pin counts.

Abstract: A method and apparatus for defining, in a computing system, the bit size of an instruction to be executed by a processing unit. Instructions are realized in the form of a plurality of memory location devices. At least one of said memory location devices, in a predetermined position, is established as a MODE bit. The MODE bit assumes a first value indicative of parallel instruction execution and assumes a second value indicative of non-parallel instruction execution.

Abstract: A method for encrypting and decrypting digital data. The digital data is initially latched by an input register. Sixteen separate cipher stages cascaded in series are used to encrypt the digital data. These cipher stages are operating at a maximum frequency limited only by the process technology. The encoded digital data from the last cipher stage is stored in an output register. The input and output registers are capable of being docked at an interface frequency that is different from that of the DES core's data frequency. After an appropriate number of cycles have elapsed, the output register is sampled. A programmable counter is used to indicate when the output register contains valid encrypted data.

Abstract: A collision avoidance technique is provided in an automated semiconductor wafer processing system, wherein a magnet or magnetic strip is incorporated into each boat or carrier used to hold and transport the semiconductor wafers during the IC fabrication process. Additionally, a magnetic field sensing device is incorporated into the robotic arm of the system for sensing the presence of magnetic fields generated by the magnet(s) incorporated into the boats and/or carriers. Using this system, it is possible for the automated system controller to determine whether an imminent collision is about to occur by monitoring changes in the detected magnetic field. In this way, collisions between one boat/carrier and a second boat/carrier may be anticipated and avoided without relying upon physical contact between the two objects in order to detect collision.

Abstract: A method of optimizing the placement of components of an integrated circuit to ensure that all circuit paths will meet their timing criteria, as well as to minimize area and total wire length is disclosed. The method employs a non-constant net weighting distribution along critical paths to encourage a mincut algorithm to place components so that path lengths are minimized as well as the entire nets coupled to paths. The magnitude of weights assigned are commensurate with the slack the path has with respect to its maximum delay constraint, as well as the level of method iteration. Any nets not deemed critical are assigned a minimum capacitance constraint to prevent them from becoming critical as a function of actual placement. Weights assigned to capacitively constrained nets are inversely proportional to the difference between the maximum capacitance allowed and the estimated capacitance of the current placement.

Abstract: A GTL input receiver for receiving differential GTL signals and for generating a CMOS output at a single-ended output terminal includes a comparator circuit, a current-to-voltage converter circuit, and an inverter. The comparator is formed of a first primary current steering device and a second primary current steering device. Auxiliary current steering devices are coupled to the first and second primary current steering devices for adding hysteresis by dynamically changing the ratio of the currents flowing through the first and second primary current source devices. The input receiver also includes a control circuit for selectively enabling and disabling the secondary current steering devices. As a result, the GTL input receiver has a hysteresis in the range of 50 mV to 200 mV and higher.

Abstract: An I/O holdoff mechanism is used to compensate for I/O device inputs being fed through a latency introducing bus. A system includes one or more I/O devices connected through a serial bus to a controller device. Each I/O device includes at least one request pin which is connected to a peripheral device. A serializer in the I/O device responds to a voltage transition occurring on any request pin of the I/O device by forwarding, in a packet over the serial bus, an indicator. The indicator indicates a current voltage on the request pin of the I/O device on which the voltage transition occurred. The controller device includes a deserializer and a bus controller. The deserializer receives the first packet and outputs a signal which indicates a current value for the voltage on the indicated request pin. The deserializer includes a busy output which indicates when the deserializer is busy and when the deserializer is idle.

Abstract: A semiconductor substrate layer is provided which includes a plurality of severed through holes (or metallized half vias) along an edge portion of the substrate layer. The bonding fingers of a leadframe are then formed into a down set (or up set) format and soldered to the substrate at the severed, plated through holes. This technique increases the contact area between the leadframe and the substrate. In addition, the down set (or up set) format of the leadframe bonding fingers decreases the stress built up due to CTE mismatch between the substrate and the leadframe.

Abstract: Scan code generation for portable personal computers (PCs) using a matrix keyboard operates to produce keyboard output scan codes corresponding to IBM.RTM. compatible PC/AT scan codes. Key numbers are assigned to one or the other of two classes (simple and complex). Two classes of scan code translation tables (simple and complex) are stored in memory, either ROM or internal RAM memory. Whenever a simple key is operated, the simple table is accessed. The complex scan code table is addressed, in accordance with a set of seven edit rules, utilized in conjunction with the state of operation of multiple keys on the keyboard, to determine the appropriate translation. All of the logic needed to generate the necessary scan codes is collapsed into a structured table-driven mechanism.

Abstract: A low-cost, moderate performance small computer system is provided by allowing a single sharable block of memory to be independently accessible as graphics or main store memory. Allocation of the memory is selected programmably, eliminating the need to have the maximum memory size for each block simultaneously. Performance penalties are minimized by dynamically allocating the memory bandwidth on demand rather than through fixed time slices. A reallocatable memory subsystem enables transparent transfer of memory function of a lower-performance memory such as DRAM to occur in conjunction with a memory upgrade to a higher-performance memory such as VRAM, for example.

Abstract: A system is employed for providing two different levels of protection for cryptographic devices transmitting digital information. The system is independent of the cryptographic algorithm used and works with any keyed cryptographic algorithm. High grade encryption is used for data transmitted from the transmitter device and employs an encryption key of "Y" bits. This information is decrypted at the receiver by a decryption circuit also having a "Y" key size. At the receiver, return information is encrypted by an encryption key having "X" bits, where X=Y-Z, with Z being a variable. The low grade information encrypted at the receiver is supplied back to the transmitter, which incorporates a decryption circuit having an "X" key size for decrypting the lower grade information.

Abstract: The present invention provides a bipolar transistor in which a lightly doped n-type hot-carrier shield extends in an epitaxial layer adjacent from a poly-emitter to an extrinsic base. This hot-carrier shield minimizes performance impairment that would otherwise occur due to a hot-carrier effect. Key steps in the method of making the bipolar transistor include a differential thermal oxidation while the poly-emitter is covered with a nitride cap. After the nitride cap is removed, an n-type dopant is implanted. The unprotected poly emitter is heavily doped. The implant partially penetrates a relatively thin oxide growth, thereby forming the hot-carrier shield. Other areas, such as the extrinsic base, and a polycrystalline base extension are covered by a relatively thick oxide growth and are unaffected by the n-type implant.

Abstract: The present invention relates to a system and method for programming VROM links. The system has an address selection circuit connected to the VROM link for selecting an address in the VROM link in which to program. A polarity control circuit is also connected to the VROM link. The polarity control circuit allows one to control the directional flow of a current used in programming the VROM link.

Abstract: The present invention relates to a power reduction digital-to-analog (DA) converter current source cell. The power reduction DA converter current source cell is comprised of a DA current source cell for sending a current to a current steering matrix and a switching means coupled to the DA current source cell for dynamically controlling the power dissipation of the DA converter current source cell when the current is not required.

Abstract: A vacuum seal for a ball junction between a low pressure chemical vapor deposition (LPCVD) chamber and a vacuum system. In one implementation, the LPCVD chamber is a quartz tube used for deposition of certain chemicals onto and into semiconductor substrates placed therein. The ball junction is formed by the combination of a ball socket coupled at the neck of the LPCVD chamber and a metal ball cover coupled to the vacuum system. In one implementation, the metal ball cover is stainless steel. In lieu of using an elastomer O-ring that can denature under certain temperature ranges, the novel vacuum seal contains a series of annular channels cut into the inside surface of a ball cover. When the ball socket is inserted into the metal ball cover, the channels are bounded by metal on three sides and by the outside surface of the ball socket on the fourth side. Each channel contains a hole coupled to a second vacuum system.

Abstract: A chemical mechanical polishing system for processing semiconductor wafers has a polishing arm and carrier assembly that press the topside surface of a semiconductor wafer against a motor driven, rotating polishing pad. Improved uniformity of material removal, as well as improved stability of material removal rate, is achieved through the use of a controller that applies a variable wafer backside pressure to the wafers being polished. More specifically, a control subsystem maintains a wafer count, corresponding to how many wafers have been polished by the polishing pad. The control subsystem regulates the backside pressure applied to each wafer in accordance with a predetermined function such that the backside pressure increases monotonically as the wafer count increases. In the preferred embodiment, the control system regulates the backside pressure in accordance with a linear function of the form: Backside Pressure=A+(B.times.Wafer Count).