Abstract: The disclosed embodiments of voltage regulators incorporate a current mode control architecture. In one embodiment, a voltage regulator includes a power switch having an input and an output. The power switch is configured to provide a first voltage during a first conduction period and a second voltage during a second conduction period. An output filter is coupled between the power switch output and an output terminal to be coupled to a load. An adjustment device is coupled to sense a current sensing voltage corresponding to a current provided to the output filter. The adjustment device is configured to convert the current sensing voltage to an adjusted current sensing voltage, including replacing a current sensing resistance associated with the current sensing voltage with a reference resistance. Control circuitry includes a current sensing input coupled to the adjustment device to sense the adjusted current sensing voltage, and an output in communication with the power switch input.

Abstract: A multiple-output DC-DC converter has a first and a second DC-DC sub-converter, each DC-DC subconverter may be a buck, boost, or buck-boost converter having a primary energy-storage inductor. Each DC-DC subconverter drives a separate output of the multiple-output converter and typically has a separate feedback control circuit for controlling output voltage and/or current. The converter has a common timing circuit to maintain a phase offset between the first and DC-DC subconverters. The primary energy storage inductors of the first and second DC-DC converter are magnetically coupled to raise an effective ripple frequency of the converter and simplify output filtering.

Abstract: An integrated circuit includes a semiconductor die including one or more switching circuits, a magnetic core having length and width, first and second metallic leads, and integrated circuit packaging material. The first metallic lead forms a first winding turn around a portion of the magnetic core, and the first metallic lead is electrically coupled to the semiconductor die. The second metallic lead forms a second winding turn around a portion of the magnetic core. The first and second winding turns are offset from each other along both of the width and length of the magnetic core. The integrated circuit is, for example, included in an integrated electronic assembly.

Abstract: A LDMOS transistor is implemented in a first impurity region on a substrate. The LDMOS transistor has a source that includes a second impurity region. The second impurity region is implanted into the surface of the substrate within the first impurity region. Additionally, the LDMOS transistor has a drain that includes a third impurity region. The third impurity region is implanted into the surface of the substrate within the first impurity region. The third impurity region is spaced a predetermined distance away from a gate of the LDMOS transistor. The drain of the LDMOS transistor further includes a fourth impurity region within the third impurity region. The fourth impurity region provides an ohmic contact for the drain.

Abstract: A multi-winding inductor includes a first foil winding and a second foil winding. One end of the first foil winding extends from a first side of the core and wraps under the core to form a solder tab under the core. One end of the second foil winding extends from a second side of the core and wraps under the core to form another solder tab under the core. Respective portions of each solder tab are laterally adjacent under the magnetic core. A coupled inductor includes a magnetic core including a first and a second end magnetic element and a plurality of connecting magnetic elements disposed between and connecting the first and second end magnetic elements. A respective first and second single turn foil winding is wound at least partially around each connecting magnetic element. Each foil winding has two ends forming respective solder tabs.

Abstract: A method of fabricating a vertical gate region in LDMOS transistor includes depositing a first masking layer on an n-well region implanted on a substrate, patterning the first masking layer to define an area, depositing a second masking layer over the area, etching through the second masking layer in a first portion of the area to expose the n-well region, and etching the exposed n-well region to form a first trench. The first trench, extending from a surface of the n-well region to a first depth, is filled with an oxide. The second masking layer is etched through in a second portion of the area to expose the n-well region. A second trench is formed in the n-well, the second trench extending from the surface to a second depth, less than the first depth. An asymmetric vertical gate is formed by filling the second trench with a conductive material.

Abstract: A transistor includes a substrate, a well formed in the substrate, a drain including a first impurity region implanted in the well, a source including a second impurity region implanted in the well and spaced apart from the first impurity region, a channel for current flow from the drain to the source, and a gate to control a depletion region between the source and the drain. The channel has an intrinsic breakdown voltage, and the well, drain and source are configured to provide an extrinsic breakdown voltage lower than the intrinsic breakdown voltage and such that breakdown occurs in a breakdown region in the well located outside the channel and adjacent the drain or the source.

Abstract: Mixers are described which allow for information sharing in redundant systems, while providing sufficient isolation between redundant system components to enable fault-tolerant operation.

Abstract: A switching power converter includes a first and second switching device, an air core coupled inductor, and a controller. The air core coupled inductor includes a first winding electrically coupled to the first switching device and a second winding electrically coupled to the second switching device. The first and second windings are magnetically coupled. The controller is operable to cause the first and second switching devices to repeatedly switch between their conductive and non-conductive states at a frequency of at least 100 kilohertz to cause current through the first and second windings to repeatedly cycle, thereby providing power to an output port. The switching power converter may have a topology including, but not limited to, a buck converter topology, a boost converter topology, and a buck-boost converter topology.

Abstract: An inductor includes a core formed of a magnetic material and a foil winding wound at least partially around or through at least a portion of the core. A first end of the winding extends away from the core to form an extended output tongue configured and arranged to supplement or serve as a substitute for a printed circuit board foil trace. A second end of the winding forms a solder tab. At least a portion of the extended output tongue and the solder tab are formed at a same height relative to a bottom surface of the core. Another inductor includes a core formed of a magnetic material, a winding wound at least partially around or through at least a portion of the core, and a ground return conductor attached to the core. The core does not form a magnetic path loop around the ground return conductor.

Abstract: The present application features methods of fabricating a gate region in a vertical laterally diffused metal oxide semiconductor (LDMOS) transistor. In one aspect, a method includes depositing a masking layer on an n-well region implanted on a substrate, patterning the masking layer to define an area, and forming a first trench in the area such that a length of the first trench extends from a surface of the n-well region to a first depth in the n-well region. The method also includes filling the first trench by a conductive material and depositing a layer of oxide over the area. The method further includes etching out at least a portion of the oxide layer to expose a portion of the conductive material, removing the conductive material from the exposed portion to form a second trench, and filling the second trench with an oxide to form an asymmetric gate of the transistor.

Abstract: A regulated, power supply system is described using multiphase DC-DC converters with dynamic fast-turnon, slow-turnoff phase shedding, early phase turn-on, and both load-voltage and drive-transistor feedback to pulsewidth modulators to provide fast response to load transients. In an embodiment, a system master can automatically determine whether all, or only some, slave phase units are fully populated. The programmable system includes fault detection with current and voltage sensing, telemetry capability, and automatic shutdown capability. In an embodiment, these are buck-type converters with or without coupled inductors, however some of the embodiments illustrated include boost configurations.

Abstract: A chip scale package implements solder bars to form a connection between a chip and a trace, formed in a substrate, such as another chip or PCB. Solder bars are formed by depositing one or more solder layers into the socket, or optionally, depositing a base metal layer into the socket and applying the solder layer to the base metal layer. The geometry of a solder bars may be rectangular, square, or other regular or irregular geometry. Solder bars provide a greater utilization of the connectivity footprint and increase the electrical and thermal flow capacity. Solder bars also provide a robust connection.

Abstract: An electric power system includes a string of N maximum power point tracking (MPPT) controllers having output ports electrically coupled in series, where N is an integer greater than one. At least one of the N MPPT controllers includes respective transistor driver circuitry powered from a power supply rail of an adjacent one of the N MPPT controllers of the string. Another MPPT controller includes an n-channel field effect freewheeling transistor electrically coupled across an output port and a resistive device electrically coupled between an input port and a gate of the freewheeling transistor, such that the freewheeling transistor operates in its conductive state when power is applied to the input port and a control subsystem of the controller is in an inactive state.

Abstract: A method for operating a maximum power point tracking (MPPT) controller including a switching circuit adapted to transfer power between an input port and an output port includes the steps of: (a) in a first operating mode of the MPPT controller, causing a first switching device of the switching circuit to operate at a fixed duty cycle; and (b) in a second operating mode of the MPPT controller, causing a control switching device of the switching circuit to repeatedly switch between its conductive and non-conductive states to maximize an amount of power extracted from a photovoltaic device electrically coupled to the input port.

Abstract: A maximum power point tracking controller includes an input port for electrically coupling to an electric power source, an output port for electrically coupling to a load, a control switching device, and a control subsystem. The control switching device is adapted to repeatedly switch between its conductive and non-conductive states to transfer power from the input port to the output port. The control subsystem is adapted to control switching of the control switching device to regulate a voltage across the input port, based at least in part on a signal representing current flowing out of the output port, to maximize a signal representing power out of the output port.

Abstract: A scalable maximum power point tracking (MPPT) controller includes an input and an output port, a switching circuit adapted to transfer power from the input port to the output port, and a controller core. The controller core is adapted to (a) control the switching circuit to maximize an amount of power extracted from a photovoltaic device electrically coupled to the input port, and (b) set one or more parameters of the MPPT controller based at least in part on a configuration code representing a number of photovoltaic cells of the photovoltaic device electrically coupled in series.

Abstract: A LDMOS transistor is implemented in a first impurity region on a substrate. The LDMOS transistor has a source that includes a second impurity region. The second impurity region is implanted into the surface of the substrate within the first impurity region. Additionally, the LDMOS transistor has a drain that includes a third impurity region. The third impurity region is implanted into the surface of the substrate within the first impurity region. The third impurity region is spaced a predetermined distance away from a gate of the LDMOS transistor. The drain of the LDMOS transistor further includes a fourth impurity region within the third impurity region. The fourth impurity region provides an ohmic contact for the drain.

Abstract: A system and method for scalable configuration of intelligent energy storage packs are disclosed. According to one embodiment, a method comprises providing a first current measurement of a first energy storage cell electrically connected to a first converter circuit, and the first converter circuit controls the charge and discharge of the first energy storage cell. A first voltage measurement of the first energy storage cell is provided. First control signals are received and the first control signals are determined according to a load policy. The first converter circuit transforms a first voltage from the first energy storage cell to a desired first bus contribution voltage according to the first control signals.

Abstract: A method of making a transistor includes etching a first side of a gate, the gate including an oxide layer formed over a substrate and a conductive material formed over the oxide layer, the etching removing a first portion of the conductive material, implanting an impurity region into the substrate such that the impurity region is self-aligned, and etching a second side of the gate to remove a second portion of the conductive material.