Abstract: An M-winding coupled inductor includes a first end magnetic element, a second end magnetic element, M connecting magnetic elements, and M windings. M is an integer greater than one. Each connecting magnetic element is disposed between and connects the first and second end magnetic elements. Each winding is wound at least partially around a respective one of the M connecting magnetic elements, and each winding has a respective leakage inductance. The coupled inductor further includes at least one top magnetic element adjacent to and extending at least partially over at least two of the M connecting magnetic elements to provide a magnetic flux path between the first and second end magnetic elements. The top magnetic element forms a gap. The inductor may be included in an M-phase power supply, and the power supply may at least partially power a computer processor.

Abstract: Disclosed are devices, apparatus, circuitry, components, mechanisms, modules, units, systems, and processes for controlling the switching frequency of a voltage regulator. Frequency monitoring and adjustment circuitry is coupled to sense a switching frequency of a power switch coupled to an output filter of the voltage regulator. The frequency monitoring and adjustment circuitry is configured to provide a frequency adjustment signal based on the sensed switching frequency. Power switch control circuitry is coupled to receive the frequency adjustment signal and is configured to control switching of the power switch based on the frequency adjustment signal.

Abstract: Disclosed are devices, apparatus, circuitry, components, mechanisms, modules, units, systems, and processes for controlling a power switch of a voltage regulator. A capacitor is coupled to an output of the power switch. Charge delivery circuitry is coupled to the capacitor and configured to provide a charging current to the capacitor. Charge control circuitry can be coupled to the charge delivery circuitry and configured to selectively allow the providing of the charging current to the capacitor.

Abstract: A power switch assembly includes a flip-chip type integrated circuit chip and a lead-frame with a plurality of spaced apart parallel lead sections. The flip-chip type integrated circuit chip includes a distributed transistor, and first and second pluralities of flip-chip interconnects connected to source and drain regions, respectively. The first and second lead sections at least partially overlap along the first axis. Each of the plurality of lead sections includes a contact portion and an extended portion extending laterally from the contact portion. The extended portions of the first and second lead section extend from the contact portion in opposite directions. The first side of the first and second lead section contacts at least two of the first and plurality of flip-chip interconnects, respectively. The second side of the first and second lead are configured to contact a first and second contact area on a printed circuit board, respectively.

Abstract: Methods and systems for monolithically fabricating a lateral double-diffused MOSFET (LDMOS) transistor having a source, drain, and a gate on a substrate, with a process flow that is compatible with a CMOS process flow are described. In some implementations, a method of fabricating a semiconductor device is provided that includes forming an LDMOS transistor having a first drain with a first drain-side n+ region, a first source with a first source-side n+ region and a first source-side p+ region, and a first gate between the first drain and the first source on the substrate. The method also includes forming an n-type CMOS transistor having a second drain having a second drain-side n+ region, a second source having a second source-side n+ region, and a second gate between the second drain and the second source. In so doing, the LDMOS transistor can be fabricated through a process that can be seamlessly integrated into a sub-micron CMOS process.

Abstract: A multiphase DC-to-DC power converter has two or more sets of input switches, each set of input switches driving primary windings of at least one associated transformer. Each transformer has one or two secondary windings, the secondary windings feeding power through output switches or rectifiers through an associated output inductor into a common filter. At least two of the output inductors are magnetically coupled.

Abstract: A multi-phase coupled inductor includes a powder core material magnetic core and first, second, third, and fourth terminals. The coupled inductor further includes a first winding at least partially embedded in the core and a second winding at least partially embedded in the core. The first winding is electrically coupled between the first and second terminals, and the second winding electrically is coupled between the third and fourth terminals. The second winding is at least partially physically separated from the first winding within the magnetic core. The multi-phase coupled inductor is, for example, used in a power supply.

Abstract: A voltage regulator is operated by, during a finite period of a voltage regular start mode having a plurality of current pulses, monotonically increasing the maximum current of the current pulses and a target voltage.

Abstract: An inductor includes a core formed of a magnetic material and a foil winding wound at least partially around or through at least a portion of the core. A first end of the winding extends away from the core to form an extended output tongue configured and arranged to supplement or serve as a substitute for a printed circuit board foil trace. A second end of the winding forms a solder tab. At least a portion of the extended output tongue and the solder tab are formed at a same height relative to a bottom surface of the core. Another inductor includes a core formed of a magnetic material, a winding wound at least partially around or through at least a portion of the core, and a ground return conductor attached to the core. The core does not form a magnetic path loop around the ground return conductor.

Abstract: A voltage regulator has a switch configured to alternately couple and decouple a voltage source through an inductor to a load, feedback circuitry to generate a feedback current, a current sensor configured to measure the feedback current, and a controller configured to receive the feedback current measurement from the current sensor and, in response thereto, to control a duty cycle of the switch. The feedback circuitry includes an amplifier having a first input configured to receive a desired voltage, a second input, and an output, a capacitor connecting the second input to the output of the amplifier, and a resistor connecting the output of the amplifier and the output terminal such that a feedback current proportional to a difference between the desired voltage and an output voltage at an output terminal flows through the resistor.

Abstract: A voltage regulator coupled to an unregulated DC input voltage source by an input terminal, and to a load by an output terminal is disclosed. The voltage regulator converts an input voltage at the input terminal to an output voltage at the output terminal. The voltage regulator includes one or more slaves, and each slave includes a switching circuit which serves as a power switch for alternately coupling and decoupling the input terminal to an intermediate node. The voltage regulator also includes a filter coupled to the slaves, the filter including one or more inductor banks each of which having a predetermined number of inductors.

Abstract: A transistor includes a source, a drain and a gate. The source includes a p-doped p-body, a p+ region overlapping the p-body, an n+ region overlapping the p-body in proximity to the p+ region, and an n-doped source, heavily double-diffused (SHDD) region, only into the source region of the transistor, the SHDD region having a depth about equal to that of the first n+ region and overlapping the first n+ region. The drain includes a second n+ region and an n-doped shallow drain overlapping the second n+ region. The gate includes a gate oxide and a conductive material over the gate oxide. The SHDD region extends further laterally than the first n+ region beneath the gate oxide. The SHDD region is implanted using a dopant concentration greater than that of the n-doped shallow drain but less than that of the first n+ region.

Abstract: A multi-winding inductor includes a first foil winding and a second foil winding. One end of the first foil winding extends from a first side of the core and wraps under the core to form a solder tab under the core. One end of the second foil winding extends from a second side of the core and wraps under the core to form another solder tab under the core. Respective portions of each solder tab are laterally adjacent under the magnetic core. A coupled inductor includes a magnetic core including a first and a second end magnetic element and a plurality of connecting magnetic elements disposed between and connecting the first and second end magnetic elements. A respective first and second single turn foil winding is wound at least partially around each connecting magnetic element. Each foil winding has two ends forming respective solder tabs.

Abstract: A semiconductor package includes a semiconductor substrate a semiconductor substrate having source and drain regions formed therein, an intermediate routing structure to provide electrical interconnects to the source and drain regions, a dielectric layer formed over the intermediate routing structure, and an under-bump-metallization (UBM) stack. The intermediate routing structure includes an outermost conductive layer, and the dielectric layer has an opening positioned over a portion of the intermediate layer routing structure. The UBM stack includes a conductive base layer formed over the dielectric layer and electrically connected to the outermost conductive layer through the opening, and a thick conductive layer formed on the base layer. A conductive bump is positioned on the UBM stack and laterally spaced from the opening.

Abstract: A method of fabricating an LDMOS transistor and a conventional CMOS transistor together on a substrate. A P-body is implanted into a source region of the LDMOS transistor. A gate oxide for the conventional CMOS transistor is formed after implanting the P-body into the source region of the LDMOS transistor. A fixed thermal cycle associated with forming the gate oxide of the conventional CMOS transistor is not substantially affected by the implanting of the P-body into the source region of the LDMOS transistor.

Abstract: An M phase coupled inductor includes a magnetic core including a first end magnetic element, a second end magnetic element, and M legs disposed between and connecting the first and second end magnetic elements. M is an integer greater than one. The coupled inductor further includes M windings, where each winding has a substantially rectangular cross section. Each one of the M windings is at least partially wound about a respective leg.

Abstract: A LDMOS transistor is implemented in a first impurity region on a substrate. The LDMOS transistor has a source that includes a second impurity region. The second impurity region is implanted into the surface of the substrate within the first impurity region. Additionally, the LDMOS transistor has a drain that includes a third impurity region. The third impurity region is implanted into the surface of the substrate within the first impurity region. The third impurity region is spaced a predetermined distance away from a gate of the LDMOS transistor. The drain of the LDMOS transistor further includes a fourth impurity region within the third impurity region. The fourth impurity region provides an ohmic contact for the drain.

Abstract: A detection circuit and one or more wires or circuit traces are included in a die. The combination is used to detect mechanical failure of the substrate, e.g. silicon after singulation of the dice from the wafer. Failures may be detected at different regions or planes within the die, and the tests may be performed during operation of the packaged die and integrated circuit, even after installation and during operation of a larger electronic device in which it is incorporated. This is especially useful for chip scale packages, but may be utilized in any type of IC package.

Abstract: Methods and structures for constructing a magnetic core of a coupled inductor. The method provides for constructing N-phase coupled inductors as both single and scalable magnetic structures, where N is an integer greater than 1. The method additionally describes how such a construction of the magnetic core may enhance the benefits of using the scalable N-phase coupled inductor. The first and second magnetic cores may be formed into shapes that, when coupled together, may form a single scalable magnetic core. For example, the cores can be fashioned into shapes such as a U, an I, an H, a ring, a rectangle, and a comb, that cooperatively form the single magnetic core.

Abstract: Methods and structures for constructing a magnetic core of a coupled inductor. The method provides for constructing N-phase coupled inductors as both single and scalable magnetic structures, where N is an integer greater than 1. The method additionally describes how such a construction of the magnetic core may enhance the benefits of using the scalable N-phase coupled inductor. The first and second magnetic cores may be formed into shapes that, when coupled together, may form a single scalable magnetic core. For example, the cores can be fashioned into shapes such as a U, an I, an H, a ring, a rectangle, and a comb, that cooperatively form the single magnetic core.