Patents Assigned to Volterra Semiconductor Corporation
  • Patent number: 8330567
    Abstract: An asymmetrical coupled inductor includes a first and a second winding and a core. The core is formed of a magnetic material and magnetically couples together the windings. The core is configured such that a leakage inductance value of the first winding is greater than a leakage inductance value of the second winding. The coupled inductor is included, for example, in a multi-phase DC-to-DC converter. A DC-to-DC converter including a symmetrical coupled inductor includes at least one additional inductor electrically coupled in series with one or more of the coupled inductor's windings. A controller for a DC-to-DC converter including a first phase having an effective inductance value greater than an effective inductance value of a second phase is configured to shut down the second phase while the first phase remains operational during a light load operating condition.
    Type: Grant
    Filed: January 14, 2010
    Date of Patent: December 11, 2012
    Assignee: Volterra Semiconductor Corporation
    Inventors: Alexandr Ikriannikov, Ognjen Djekic
  • Publication number: 20120293017
    Abstract: Disclosed are systems, devices, circuits, components, mechanisms, and processes in which a switching mechanism can be coupled between components. The switching mechanism is configured to have an on state or an off state, where the on state allows current to pass along a current path. A monitoring mechanism has one or more sensing inputs coupled to sense an electrical characteristic at the current path. The electrical characteristic can be a current, voltage, and/or power by way of example. The monitoring mechanism is configured to output a reporting signal indicating the sensed electrical characteristic. The monitoring mechanism can be integrated with the switching mechanism on a chip.
    Type: Application
    Filed: April 23, 2012
    Publication date: November 22, 2012
    Applicant: VOLTERRA SEMICONDUCTOR CORPORATION
    Inventors: David Lidsky, Ognjen Djekic, Ion Opris, Budong You, Anthony J. Stratakos, Alexander Ikriannikov, Biljana Beronja, Trey Roessig
  • Patent number: 8314461
    Abstract: Methods and systems for monolithically fabricating a lateral double-diffused MOSFET (LDMOS) transistor having a source, drain, and a gate on a substrate, with a process flow that is compatible with a CMOS process flow are described.
    Type: Grant
    Filed: December 5, 2011
    Date of Patent: November 20, 2012
    Assignee: Volterra Semiconductor Corporation
    Inventors: Budong Yu, Marco A. Zuniga
  • Patent number: 8299882
    Abstract: An inductor includes a core formed of a magnetic material and a foil winding wound at least partially around or through at least a portion of the core. A first end of the winding extends away from the core to form an extended output tongue configured and arranged to supplement or serve as a substitute for a printed circuit board foil trace. A second end of the winding forms a solder tab. At least a portion of the extended output tongue and the solder tab are formed at a same height relative to a bottom surface of the core. Another inductor includes a core formed of a magnetic material, a winding wound at least partially around or through at least a portion of the core, and a ground return conductor attached to the core. The core does not form a magnetic path loop around the ground return conductor.
    Type: Grant
    Filed: November 5, 2010
    Date of Patent: October 30, 2012
    Assignee: Volterra Semiconductor Corporation
    Inventor: Alexandr Ikriannikov
  • Patent number: 8299885
    Abstract: An M phase coupled inductor includes a magnetic core including a first end magnetic element, a second end magnetic element, and M legs disposed between and connecting the first and second end magnetic elements. M is an integer greater than one. The coupled inductor further includes M windings, where each winding has a substantially rectangular cross section. Each one of the M windings is at least partially wound about a respective leg.
    Type: Grant
    Filed: May 13, 2011
    Date of Patent: October 30, 2012
    Assignee: Volterra Semiconductor Corporation
    Inventors: Alexandr Ikriannikov, Anthony Stratakos, Charles R. Sullivan, Aaron M. Schultz, Jieli Li
  • Patent number: 8294544
    Abstract: An M-phase coupled inductor including a magnetic core and M windings, where M is an integer greater than one. The magnetic core is formed of a core material, and the magnetic core includes a first outer leg forming a first gap. The first gap includes a first gap material having lower magnetic permeability than the core material. Each winding is wound at least partially around at least a portion of the magnetic core, and each winding has a respective leakage inductance. The first gap causes the leakage inductances to be greater than if the first outer leg did not form the first gap. The coupled inductor may be used in a power supply, and the power supply may be used in a computing apparatus.
    Type: Grant
    Filed: March 16, 2009
    Date of Patent: October 23, 2012
    Assignee: Volterra Semiconductor Corporation
    Inventors: Alexandr Ikriannikov, Anthony Stratakos
  • Patent number: 8283902
    Abstract: A voltage regulator has a switch configured to alternately couple and decouple a voltage source through an inductor to a load, feedback circuitry to generate a feedback current, a current sensor configured to measure the feedback current, and a controller configured to receive the feedback current measurement from the current sensor and, in response thereto, to control a duty cycle of the switch. The feedback circuitry includes an amplifier having a first input configured to receive a desired voltage, a second input, and an output, a capacitor connecting the second input to the output of the amplifier, and a resistor connecting the output of the amplifier and the output terminal such that a feedback current proportional to a difference between the desired voltage and an output voltage at an output terminal flows through the resistor.
    Type: Grant
    Filed: September 12, 2011
    Date of Patent: October 9, 2012
    Assignee: Volterra Semiconductor Corporation
    Inventors: Seth Kahn, Michael D. McJimsey
  • Patent number: 8253420
    Abstract: A detection circuit and one or more wires or circuit traces are included in a die. The combination is used to detect mechanical failure of the substrate, e.g. silicon after singulation of the dice from the wafer. Failures may be detected at different regions or planes within the die, and the tests may be performed during operation of the packaged die and integrated circuit, even after installation and during operation of a larger electronic device in which it is incorporated. This is especially useful for chip scale packages, but may be utilized in any type of IC package.
    Type: Grant
    Filed: December 4, 2009
    Date of Patent: August 28, 2012
    Assignee: Volterra Semiconductor Corporation
    Inventors: Charles Nickel, Katherine Nickel, legal representative, David Lidsky, Seth Kahn
  • Patent number: 8237530
    Abstract: An M-winding coupled inductor includes a first end magnetic element, a second end magnetic element, M connecting magnetic elements, and M windings. M is an integer greater than one. Each connecting magnetic element is disposed between and connects the first and second end magnetic elements. Each winding is wound at least partially around a respective one of the M connecting magnetic elements. The coupled inductor further includes at least one top magnetic element adjacent to and extending at least partially over at least two of the M connecting magnetic elements to provide a magnetic flux path between the first and second end magnetic elements. The inductor may be included in an M-phase power supply, and the power supply may at least partially power a computer processor.
    Type: Grant
    Filed: July 6, 2010
    Date of Patent: August 7, 2012
    Assignee: Volterra Semiconductor Corporation
    Inventor: Alexandr Ikriannikov
  • Patent number: 8233306
    Abstract: Methods, systems, and apparatus, including computer program products for programming memory. In one aspect, a program circuit includes a first transistive element; a second transistive element coupled to a first end of the first transistive element; a burn subcircuit, the burn subcircuit including a third transistive element coupled to a fourth transistive element, where the drain of the third transistive element is coupled to a second end of the first transistive element, and the source of the third transistive element is coupled to the drain of the fourth transistive element; and a fifth transistive element coupled in parallel to the fourth transistive element. Control logic coupled to the first transistive element, the burn subcircuit, and the fourth transistive element selectively enables the second transistive element, selectively enables the fourth transistive element, and selectively enables the fifth transistive element to enable a read mode or a program mode.
    Type: Grant
    Filed: March 31, 2010
    Date of Patent: July 31, 2012
    Assignee: Volterra Semiconductor Corporation
    Inventor: Marco A. Zuniga
  • Patent number: 8174348
    Abstract: Two-phase coupled inductors including a magnetic core, at least a first winding, and at least three solder tabs. Power supplies including a printed circuit board, a two-phase coupled inductor affixed to the printed circuit board, and first and second switching circuits affixed to the printed circuit board. Each of the first and second switching circuits are electrically coupled to a respective solder tab of the two-phase coupled inductor affixed to the printed circuit board.
    Type: Grant
    Filed: May 24, 2010
    Date of Patent: May 8, 2012
    Assignee: Volterra Semiconductor Corporation
    Inventor: Alexandr Ikriannikov
  • Patent number: 8169081
    Abstract: An integrated circuit structure includes a first conductive layer and an under bump metallization layer over the first conductive layer. The first conductive layer has a first conductive region and a second conductive region electrically isolated from the first conductive region. The under bump metallization layer has a first conductive area and a second conductive area electrically isolated from the first conductive area, the first conductive area substantially located over the first conductive region and the second conductive area substantially located over the second conductive region. At least one of the first conductive area or the first conductive region includes a first protrusion extending toward the second conductive area or second conductive region, respectively. Conductive vias connect the first conductive region to the second conductive area and connect the second conductive region to the first conductive area, and the vias include at least one via connected to the first protrusion.
    Type: Grant
    Filed: December 23, 2008
    Date of Patent: May 1, 2012
    Assignee: Volterra Semiconductor Corporation
    Inventors: Ilija Jergovic, Efren M. Lacap
  • Publication number: 20120074492
    Abstract: Methods and systems for monolithically fabricating a lateral double-diffused MOSFET (LDMOS) transistor having a source, drain, and a gate on a substrate, with a process flow that is compatible with a CMOS process flow are described.
    Type: Application
    Filed: December 5, 2011
    Publication date: March 29, 2012
    Applicant: VOLTERRA SEMICONDUCTOR CORPORATION
    Inventors: Budong Yu, Marco A. Zuniga
  • Publication number: 20120044014
    Abstract: An integrated circuit chip includes a first input port, a first output port, and first and second transistors electrically coupled in series across the first input port. The second transistor is also electrically coupled across the first output port and is adapted to provide a path for current flowing through the first output port when the first transistor is in its non-conductive state. The integrated circuit chip additionally includes first driver circuitry for driving gates of the first and second transistors to cause the transistors to switch between their conductive and non-conductive states. The integrated circuit chip further includes first controller circuitry for controlling the first driver circuitry such that the first and second transistors switch between their conductive and non-conductive states to at least substantially maximize an amount of electric power extracted from an electric power source electrically coupled to the first input port.
    Type: Application
    Filed: August 17, 2011
    Publication date: February 23, 2012
    Applicant: VOLTERRA SEMICONDUCTOR CORPORATION
    Inventors: Anthony J. Stratakos, Michael D. McJimsey, Ilija Jergovic, Alexandr Ikriannikov, Artin Der Minassians, Kaiwei Yao, David B. Lidsky, Marco A. Zuniga, Ana Borisavljevic
  • Publication number: 20120043823
    Abstract: A switching circuit for extracting power from an electric power source includes (1) an input port for electrically coupling to the electric power source, (2) an output port for electrically coupling to a load, (3) a first switching device configured to switch between its conductive state and its non-conductive state to transfer power from the input port to the output port, (4) an intermediate switching node that transitions between at least two different voltage levels at least in part due to the first switching device switching between its conductive state and its non-conductive state, and (5) a controller for controlling the first switching device to maximize an average value of a voltage at the intermediate switching node.
    Type: Application
    Filed: August 17, 2011
    Publication date: February 23, 2012
    Applicant: VOLTERRA SEMICONDUCTOR CORPORATION
    Inventors: Anthony J. Stratakos, Michael D. McJimsey, Ilija Jergovic, Alexandr Ikriannikov, Artin Der Minassians, Kaiwei Yao, David B. Lidsky, Marco A. Zuniga, Ana Borisavljevic
  • Publication number: 20120043818
    Abstract: An electric power system includes N electric power sources and N switching circuits, where N in an integer greater than one. Each switching circuit includes an input port electrically coupled to a respective one of the N electric power sources, an output port, and a first switching device adapted to switch between its conductive and non-conductive states to transfer power from the input port to the output port. The output ports of the N switching circuits are electrically coupled in series and to a load to establish an output circuit. Each of the N switching circuits uses an interconnection inductance of the output circuit as a primary energy storage inductance of the switching circuit.
    Type: Application
    Filed: August 17, 2011
    Publication date: February 23, 2012
    Applicant: VOLTERRA SEMICONDUCTOR CORPORATION
    Inventors: Anthony J. Stratakos, Michael D. McJimsey, Ilija Jergovic, Alexandr Ikriannikov, Artin Der Minassians, Kaiwei Yao, David B. Lidsky, Marco A. Zuniga, Ana Borisavljevic
  • Patent number: 8120342
    Abstract: A voltage regulator includes a switch configured to alternately couple and decouple a voltage source through a inductor to a load, a feedback circuitry configured to generate a feedback current proportional to a difference between a desired voltage and an output voltage at an output terminal, a current sensor configured to measure the feedback current, a controller configured to receive the feedback current level from the current sensor and, in response thereto, to control a duty cycle of the switch, and a current mirror configured to generate a reporting current proportional to the feedback current.
    Type: Grant
    Filed: May 6, 2009
    Date of Patent: February 21, 2012
    Assignee: Volterra Semiconductor Corporation
    Inventors: Seth Kahn, Michael D. McJimsey
  • Publication number: 20120025799
    Abstract: The disclosed embodiments of voltage regulators incorporate a current mode control architecture. In one embodiment, a comparator mechanism triggers a transition in a power switch when the error in the regulated output voltage is equal to a proportionally scaled value of current provided at an output filter. The voltage regulator includes a power switch having an input and an output. The power switch is configured to provide a first voltage during a first conduction period and a second voltage during a second conduction period. An output filter is coupled between the power switch output and an output terminal to be coupled to a load. A comparator mechanism has a reference input coupled to a reference voltage, a feedback input coupled to sense a feedback voltage at the output filter, a current sensing input coupled to sense a current sensing voltage corresponding to a current provided to the output filter, and an output in communication with the power switch input.
    Type: Application
    Filed: October 14, 2010
    Publication date: February 2, 2012
    Applicant: VOLTERRA SEMICONDUCTOR CORPORATION
    Inventors: David Christian Gerard Tournatory, Seth Kahn
  • Publication number: 20120025796
    Abstract: The disclosed embodiments of voltage regulators incorporate a current mode control architecture. In one embodiment, a voltage regulator includes a power switch having an input and an output. The power switch is configured to provide a first voltage during a first conduction period and a second voltage during a second conduction period. An output filter is coupled between the power switch output and an output terminal to be coupled to a load. An adjustment device is coupled to sense a current sensing voltage corresponding to a current provided to the output filter. The adjustment device is configured to convert the current sensing voltage to an adjusted current sensing voltage, including replacing a current sensing resistance associated with the current sensing voltage with a reference resistance. Control circuitry includes a current sensing input coupled to the adjustment device to sense the adjusted current sensing voltage, and an output in communication with the power switch input.
    Type: Application
    Filed: October 14, 2010
    Publication date: February 2, 2012
    Applicant: VOLTERRA SEMICONDUCTOR CORPORATION
    Inventor: Seth Kahn
  • Patent number: 8106516
    Abstract: A chip scale package implements solder bars to form a connection between a chip and a trace, formed in a substrate, such as another chip or PCB. Solder bars are formed by depositing one or more solder layers into the socket, or optionally, depositing a base metal layer into the socket and applying the solder layer to the base metal layer. The geometry of a solder bars may be rectangular, square, or other regular or irregular geometry. Solder bars provide a greater utilization of the connectivity footprint and increase the electrical and thermal flow capacity. Solder bars also provide a robust connection.
    Type: Grant
    Filed: July 27, 2010
    Date of Patent: January 31, 2012
    Assignee: Volterra Semiconductor Corporation
    Inventors: Efren M. Lacap, Subhash Rewachand Nariani, Charles Nickel