Method for determining native threshold voltage of nonvolatile memory
A method for determining native threshold voltage of nonvolatile memory includes following steps. A memory cell including a control gate, a charge storage layer, a source region, and a drain region is provided. A programming operation is performed on the memory cell by using F-N tunneling effect to obtain a programming curve of time versus threshold voltage. In the programming operation, a positive voltage is applied to the control gate. An erase operation is performed on the memory cell by using F-N tunneling effect to obtain an erasure curve of time versus threshold voltage. In the erase operation, a negative voltage is applied to the control gate. The absolute values of the positive voltage and the negative voltage are the same. The native threshold voltage of memory cell is determined from the cross point of the programming curve and the erasure curve.
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1. Field of the Invention
The present invention relates to a method of determining a semiconductor memory device. More particularly, the present invention relates to a method of determining a native threshold voltage of a nonvolatile memory.
2. Description of Related Art
A typical flash memory has a floating gate and a control gate fabricated using doped polysilicon. When the memory is programmed, suitable programmed voltages are applied to the source region, the drain region, and the control gate respectively. Next, electrons will flow from the source region to the drain region through channel of memory cell. In the process, a portion of the electrons will penetrate a tunneling oxide layer below the polysilicon floating gate layer. Here, the electrons enter and distribute uniformly in the entire polysilicon floating gate layer. The phenomenon of electrons penetrating the tunneling oxide layer to enter the polysilicon floating gate layer is called a tunneling effect. The tunneling effect can be categorized into a channel hot-electron injection and a Fowler-Nordheim tunneling (F-N tunneling). The flash memory is usually programmed with the channel hot-electron injection, and erased with the F-N tunneling by passing the channel region or the side of the source region.
In general, after the flash memory has been manufactured, as each memory cell may be affected by the manufacturing process to result in uneven threshold voltages, the memory will have a larger distribution of the threshold voltages that may cause difficulty in use. Hence, before the shipment, the UV light is usually applied to irradiate the flash memory completely, such that every memory cell of the flash memory is at a stage of low threshold voltage (Low |Vt|) to achieve an initialization of devices. After the memory cell has been irradiated completely by the UV light, the threshold voltage maintained is referred as a native threshold voltage.
However, in the trend of increasing the integration of memory devices, the size of memory cells is also relatively decreased. Moreover, the memory cell is usually covered by high metal density. When the memory is exposed to the UV light, the UV light is blocked by metal layers, so the memory cell will not be irradiated easily. Consequently, the initialization of devices in the memory can not be accomplished. Furthermore, as the UV light can not irradiate the memory cell completely, the memory cell can not reach the stage of the native threshold voltage and the native threshold voltage of the memory cell can not be determined.
SUMMARY OF THE INVENTIONThe present invention provides a method of determining a native threshold voltage of a nonvolatile memory, where the native threshold voltage of the nonvolatile memory can be easily determined.
The present invention provides a method of determining a native threshold voltage of a nonvolatile memory. The method includes the following steps. Firstly, a memory cell having a control gate, a charge storage layer, a source region, and a drain region is provided. Next, a programming operation is performed on the memory cell by using an F-N tunneling effect to obtain a programming curve of time versus threshold voltage. In the programming operation, a first voltage is applied to the control gate. Thereafter, an erase operation is performed on the memory cell by using the F-N tunneling effect to obtain an erasure curve of time versus threshold voltage. In the erase operation, a second voltage is applied to the control gate. Here, the absolute values of the second voltage and the first voltage are the same, but the polarities are opposite. Finally, the native threshold voltage of the memory cell is determined from a cross point of the programming curve and the erasure curve.
In one embodiment of the present invention, the first voltage is between 8V and 20V.
In one embodiment of the present invention, the second voltage is between −8V and −20V.
In one embodiment of the present invention, the source region and the drain region are grounded or applied with a voltage of 0V in the programming operation.
In one embodiment of the present invention, the source region and the drain region are grounded or applied with a voltage of 0V in the erase operation.
In one embodiment of the present invention, the memory cell is a flash memory cell.
In light of the foregoing, since the method of determining the native threshold voltage of the nonvolatile memory in the present invention only requires one programming operation and one erase operation, thus, the method in the present invention can determine the native threshold voltage of the nonvolatile memory easily. Furthermore, the native threshold voltage of the memory cell can still be easily determined when the memory cell is covered with a high-density metal layer.
In order to make the aforementioned and other features and advantages of the present invention more comprehensible, several embodiments accompanied with figures are described in detail below.
The accompanying drawings are included to provide a further understanding of the invention, and are incorporated in and constitute a part of this specification. The drawings illustrate embodiments of the invention and, together with the description, serve to explain the principles of the invention.
Referring to
The tunneling dielectric layer 102, the charge storage layer 104, the inter-gate dielectric layer 106, and the control gate 108 are sequentially disposed on the substrate 100, for example. Moreover, a material of the tunneling dielectric layer 102 is, for example, silicon oxide. A material of the charge storage layer 104 includes, for example, doped polysilicon. Furthermore, a material of the inter-gate dielectric layer 106 is, for example, silicon oxide or silicon oxide/silicon nitride/silicon oxide. The source region 110 and the drain region 112 are disposed within the substrate 100 at the two sides of the gate 108.
Referring to
Referring to
Furthermore, as illustrated in
The curves of experiments 1-3 are illustrated in
Referring to
Next, a programming operation is performed on the memory cell by using an F-N tunneling effect to obtain a programming curve of time versus threshold voltage. In the programming operation, as illustrated in
Thereafter, an erase operation is performed on the memory cell (step 204) by using the F-N tunneling effect to obtain an erasure curve of time versus threshold voltage. In the erase operation, as illustrated in
Moreover, the native threshold voltage of the memory cell is determined from a cross point of the programming curve and the erasure curve (step 206).
Subsequently, the effectiveness of the method of determining the native threshold voltage of the nonvolatile memory in the present invention is illustrated according to the experiments.
In experiment 1, the programming voltage is +18V, and the programming curve is shown (symbol ●); the erase voltage is −18V, and the erasure curve is displayed (symbol □).
In experiment 2, the programming voltage is +17V, and the programming curve is shown (symbol Δ); the erase voltage is −17V, and the erasure curve is displayed (symbol ×).
In experiment 3, the programming voltage is +16V, and the programming curve is shown (symbol ▴); the erase voltage is −16V, and the erasure curve is displayed (symbol ∘).
In experiment 4, the programming voltage is +15V, and the programming curve is shown (symbol ⋄); the erase voltage is −15V, and the erasure curve is displayed (symbol ▪).
As illustrated in
Based on the results of experiments 1-4, the threshold voltage values (2.52V, 2.5V, 2.49V, 2.5V) corresponding to the cross points A, B, C, D of the programming curve and the erasure curve are very close to the native threshold voltage value (2.5V) of the memory cell. Hence, the native threshold voltage of the nonvolatile memory can be easily determined by using the method of the present invention.
In summary, the method of determining the native threshold voltage of the nonvolatile memory in the present invention utilizes the F-N tunneling effect to perform a programming operation and an erase operation. Thereafter, a relationship of time versus threshold voltage is obtained from the programming operation and the erase operation. Herein, the native threshold voltage of the memory can be easily determined from the cross point of the programming curve and the erasure curve. As only one programming operation and one erasure operation are performed, the native threshold voltage of the nonvolatile memory can be determined easily by using the method of the present invention.
Although the present invention has been described with reference to the above embodiments, it will be apparent to one of the ordinary skill in the art that modifications to the described embodiment may be made without departing from the spirit of the invention. Accordingly, the scope of the invention will be defined by the attached claims not by the above detailed descriptions.
Claims
1. A method of determining a native threshold voltage of a nonvolatile memory, comprising:
- providing a memory cell, wherein the memory cell comprises a control gate, a charge storage layer, a source region, and a drain region;
- performing a programming operation on the memory cell by using a Fowler-Nordheim tunneling effect to obtain a programming curve of time versus threshold voltage, and applying a first voltage to the control gate in the programming operation;
- performing an erase operation on the memory cell by using the Fowler-Nordheim tunneling effect to obtain an erasure curve of time versus threshold voltage, and applying a second voltage to the control gate in the erase operation, wherein absolute values of the second voltage and the first voltage are the same, but polarities of the second voltage and the first voltage are opposite; and
- determining the native threshold voltage of the memory cell from a cross point of the programming curve and the erasure curve.
2. The method of determining the native threshold voltage of the nonvolatile memory as claimed in claim 1, wherein the first voltage is between 8V and 20V.
3. The method of determining the native threshold voltage of the nonvolatile memory as claimed in claim 1, wherein the second voltage is between −8V and −20V.
4. The method of determining the native threshold voltage of the nonvolatile memory as claimed in claim 1, wherein the source region and the drain region are grounded or applied with a voltage of 0V in the programming operation.
5. The method of determining the native threshold voltage of the nonvolatile memory as claimed in claim 1, wherein the source region and the drain region are grounded or applied with a voltage of 0V in the erase operation.
6. The method of determining the native threshold voltage of the nonvolatile memory as claimed in claim 1, wherein the memory cell is a flash memory cell.
6768165 | July 27, 2004 | Eitan |
7123532 | October 17, 2006 | Lusky et al. |
20060227608 | October 12, 2006 | Lusky |
20070258289 | November 8, 2007 | Lue |
Type: Grant
Filed: Apr 17, 2009
Date of Patent: Jan 11, 2011
Patent Publication Number: 20100265774
Assignee: Windbond Electronics Corp. (Taichung County)
Inventors: Chao-Hua Chang (Taichung County), Chien-Min Wu (Hsinchu)
Primary Examiner: Son L Mai
Attorney: J.C. Patents
Application Number: 12/425,650
International Classification: G11C 16/04 (20060101);