Patents Assigned to Xilinx, Inc.
  • Patent number: 10979034
    Abstract: A circuit includes a master latch circuit and a slave latch circuit. The master latch circuit is configured to receive an input data signal associated with an input data voltage domain and generate a first output data signal associated with an output data voltage domain different from the input data voltage domain. The slave latch circuit is configured to receive, from the master latch circuit, the first output data signal and generate a second output data associated with the output data voltage domain.
    Type: Grant
    Filed: June 19, 2018
    Date of Patent: April 13, 2021
    Assignee: XILINX, INC.
    Inventors: Kumar Rahul, Santosh Yachareni, Jitendra Kumar Yadav, Md Nadeem Iqbal, Teja Masina, Sourabh Swarnkar, Suresh Babu Kotha
  • Patent number: 10977051
    Abstract: Some examples described herein provide for dynamically reconfiguring a base address register (BAR) of a Peripheral Component Interconnect Express (PCIe) configuration space. In an example, information relating to a BAR of a PCIe configuration space is written to a PCIe extended configuration space of the PCIe configuration space, which is read, by a dynamic BAR module. Respective values are written, by the dynamic BAR module, to bits of the BAR based on the information. After writing by the dynamic BAR module, a set value is attempted to be written to each of address bits of the BAR. Writing the set value to an address bit of the BAR is prevented when the address bit is set to a predefined value. After attempting to write, a read value is read from the bits of the BAR. A base address of memory is written to the BAR based on the read value.
    Type: Grant
    Filed: November 8, 2019
    Date of Patent: April 13, 2021
    Assignee: XILINX, INC.
    Inventors: Christopher Y. Karman, Vidya Gopalakrishnan, Ramesh Barukula
  • Patent number: 10978167
    Abstract: A disclosed circuit arrangement includes a bank of efuse cells, first and second sense amplifiers coupled to input signals representing constant logic-1 and logic-0 values, respectively, a storage circuit, an efuse control circuit, and an efuse security circuit. The efuse control circuit inputs signals from the bank of efuse cells and signals that are output from the first and second sense amplifiers, and stores data representative of values of the signals in the storage circuit. The efuse security reads the data from the storage circuit and generates an alert signal having a state that indicates a security violation in response to data representative of the value of the signal from the first sense amplifier indicating a logic-0 value or data representative of the value of the signal from the second sense amplifier indicating a logic-1 value.
    Type: Grant
    Filed: March 2, 2020
    Date of Patent: April 13, 2021
    Assignee: XILINX, INC.
    Inventors: James D. Wesselkamper, Edward S. Peterson, Jason J. Moore, Steven E. McNeil
  • Patent number: 10977018
    Abstract: Implementing an application within a heterogeneous device can include receiving an application specifying a plurality of hardware accelerators and having a plurality of sections corresponding to different subsystems of the heterogeneous device, wherein the plurality of sections are specified using different programming models. Compiling each section based on the programming model of the section and the subsystem of the heterogeneous device corresponding to the section into an accelerator representation. Linking the accelerator representations based on a platform of the heterogeneous device, generating a hardware implementation of the application for the heterogeneous device based on the linked accelerator implementations, and automatically generating program code configured to control one or more of the plurality of hardware accelerators of the hardware implementation.
    Type: Grant
    Filed: December 5, 2019
    Date of Patent: April 13, 2021
    Assignee: Xilinx, Inc.
    Inventors: L. James Hwang, Michael Gill, Tom Shui, Jorge E. Carrillo, Alfred Huang, Sudipto Chakraborty
  • Patent number: 10969433
    Abstract: Apparatus and associated methods relate to compacting scan chain output responses of vectors into an on-chip multiple-input shift register (MISR) in the presence of unknown/indeterministic values X in design. In an illustrative example, a system may include a processing engine configured to generate a control signal for a MISR, and the control signal may hold information of what cycle has deterministic output response. The MISR may be configured to compact deterministic output responses of actual scan chain output responses in response to the decoded control signal and compare on-chip MISR signatures with expected MISR signatures to generate pass/fail status of the test. By using the system, unknown/indeterministic values X on the output responses may be blocked from being compacted into the MISR. Accordingly, the on-chip MISR signatures may not be corrupted by the unknown/indeterministic values X, and accuracy of the scan test may be advantageously improved.
    Type: Grant
    Filed: August 28, 2019
    Date of Patent: April 6, 2021
    Assignee: XILINX, INC.
    Inventors: Rambabu Nerukonda, Ismed D. Hartanto, Aaron K. Mathew
  • Patent number: 10970217
    Abstract: Embodiments disclosed herein provide a domain aware data migration scheme between processing elements, memory, and various caches in a CC-NUMA system. The scheme creates domain awareness in data migration operations, such as Direct Cache Transfer (DCT) operation, stashing operation, and in the allocation of policies of snoop filters and private, shared, or inline caches. The scheme defines a hardware-software interface to communicate locality information (also referred herein as affinity information or proximity information) and subsequent hardware behavior for optimal data migration, thus overcoming traditional CC-NUMA limitations.
    Type: Grant
    Filed: May 24, 2019
    Date of Patent: April 6, 2021
    Assignee: XILINX, INC.
    Inventors: Jaideep Dastidar, Millind Mittal
  • Patent number: 10971474
    Abstract: A chip package and method of fabricating the same are described herein. The chip package generally includes a stand-off which spaces a die from a substrate to control the collapse of a solder joint coupling the die to the substrate.
    Type: Grant
    Filed: March 1, 2019
    Date of Patent: April 6, 2021
    Assignee: XILINX, INC.
    Inventors: Jaspreet Singh Gandhi, Henley Liu
  • Patent number: 10969821
    Abstract: Methods and apparatus for tracking delay in signals sent from a first clock domain to a second clock domain are disclosed. For example, at a first time a common timing reference signal (SysRef) may be received at the first clock domain, and a latency marker may be input into a first-in first-out data structure (FIFO) coupling the first clock domain to the second clock domain. At a second time, the SysRef may be received at the second clock domain, and a timer may be started at the second clock domain. At a third time, the latency marker may be received from the FIFO at the second clock domain, and the counter may be stopped at a final count. A FIFO latency may be determined based on the final count and on a difference between the second time and the first time.
    Type: Grant
    Filed: May 29, 2018
    Date of Patent: April 6, 2021
    Assignee: XILINX, INC.
    Inventors: Ryan Kinnerk, Bob W. Verbruggen, John E. McGrath
  • Patent number: 10962588
    Abstract: A device comprising a plurality of transistors; interconnect elements coupled to the plurality of transistors is described. The interconnect elements enable the transfer of signals between the plurality of transistors. The device further includes a cooling element associated with the device, wherein the cooling element is configured to maintain a temperature of a circuit having the plurality of transistors and interconnect elements below a predetermined temperature; wherein one or more parameters of the device is optimized to operate at a temperature below the predetermined temperature. A method of implementing a circuit is also described.
    Type: Grant
    Filed: July 20, 2018
    Date of Patent: March 30, 2021
    Assignee: XILINX, INC.
    Inventor: Michael J. Hart
  • Patent number: 10963460
    Abstract: Integrated circuits and methods relating to hardware acceleration include independent, programmable, and parallel processing units (PU) custom-adapted to process a data stream and aggregate the results to respond to a query. In an illustrative example, a data stream from a database may be divided into data blocks and allocated to a corresponding PU. Each data block may be processed by one of the PUs to generate results according to a predetermined instruction set. A concatenate unit may merge and concatenate a result of each data block together to generate an output result for the query. In some embodiments, very large database SQL queries, for example, may be accelerated by hardware PU/concatenate engines implemented in fixed ASIC or reconfigurable FPGA hardware circuitry.
    Type: Grant
    Filed: December 6, 2018
    Date of Patent: March 30, 2021
    Assignee: XILINX, INC.
    Inventors: Hare K. Verma, Bing Tian
  • Patent number: 10963421
    Abstract: Embodiments herein describe a SoC that includes a mapper that identifies a destination ID for routing a transaction through a NoC. In one embodiment, the NoC includes ingress and egress logic blocks which permit hardware elements in the SoC to transmit and receive data using the NoC. In one embodiment, the ingress logic blocks can include the mapper that identifies a destination ID for each transaction. In one embodiment, the mapper can receive a destination ID from the hardware element that submitted the transaction to the ingress logic block. In this case, the mapper can bypass the address map by using the provided destination ID. If a destination ID is not provided, however, the mapper can use an address provided in the transaction to identify the destination ID.
    Type: Grant
    Filed: April 27, 2018
    Date of Patent: March 30, 2021
    Assignee: XILINX, INC.
    Inventor: Ian A. Swarbrick
  • Patent number: 10963746
    Abstract: Embodiments herein describe, when executing an average pooling operation in a neural network, scaling input operands before performing an accumulate operation. Performing average pooling in a neural network averages the values in each face of a 3D volume, thereby downsampling or subsampling the data. This can be performed by adding all the values in a face and then dividing the total accumulated value by the total values in the face. However, the order of operations in a multiply-accumulator (MAC) is reversed from the order of operations for performing average pooling. To more efficiently use the MAC, the order of operations when performing average pooling is reversed so that determining the average value for a face can be performed on a single MAC. To do so, the values in the face are first scaled by a multiplier before being summed by an accumulator.
    Type: Grant
    Filed: January 14, 2019
    Date of Patent: March 30, 2021
    Assignee: XILINX, INC.
    Inventor: Andrew M. Whyte
  • Patent number: 10963170
    Abstract: Embodiments herein describe a reconfigurable integrated circuit (IC) where data can be retained in memory when performing a partial reconfiguration. Partial reconfiguration includes reconfiguring programmable logic in the IC while certain functions of the IC remain operational or active. In one embodiment, the reconfigurable IC includes control logic for saving or retaining data in the IC during a partial reconfiguration. That is, rather than clearing the memory elements, the user can specify that the memory blocks containing certain data should be retained while the other memory blocks can be cleared. In this manner, the data can be retained in the IC during a partial reconfiguration which saves time, power, and cost. Once partial reconfiguration is complete, the newly configured programmable logic can retrieve and process the saved data from the on-chip memory.
    Type: Grant
    Filed: January 30, 2019
    Date of Patent: March 30, 2021
    Assignee: XILINX, INC.
    Inventors: Subodh Kumar, David P. Schultz, Weiguang Lu, Michelle Zeng
  • Patent number: 10963411
    Abstract: Programmable devices and methods of operation are disclosed. In some embodiments, a programmable device may include programmable logic selectively coupled to a plurality of input/output (I/O) interface circuits by a programmable interconnect fabric and a network-on-chip (NoC) interconnect system. The programmable logic may include configurable logic elements, programmable interconnects, and dedicated circuitry. The programmable interconnects may form part of the programmable interconnect fabric. In some embodiments, the programmable interconnect fabric selectively routes non-packetized data between the programmable logic and a first group of I/O interface circuits, and the NoC interconnect system selectively routes packetized data between the programmable logic and a second group of I/O interface circuits. The NoC interconnect system may operate according to a data packet protocol, and the second group of I/O interface circuits may include memory controllers compatible with the data packet protocol.
    Type: Grant
    Filed: July 3, 2019
    Date of Patent: March 30, 2021
    Assignee: XILINX, INC.
    Inventors: Martin L. Voogel, Trevor J. Bauer, Rafael C. Camarota
  • Patent number: 10963615
    Abstract: Some examples described herein relate to routing in routing elements. In an example, a design system includes a processor and a memory, storing instruction code, coupled to the processor. The processor is configured to execute the instruction code to model a communication network comprising switches interconnected in an array of data processing engines (DPEs), generate global routes of nets in the modeled communication network, generate detailed routes of the nets using the global routes, and translate the detailed routes to a file. Each of the switches has multiple input or output channels connected to another switch that are modeled as a single input or output edge, respectively, connected to the other switch. Each global route is generated through edge(s) of the switches. Each detailed route is generated comprising identifying one of the multiple input or output channels modeled by each edge through which the respective global route is generated.
    Type: Grant
    Filed: April 30, 2019
    Date of Patent: March 30, 2021
    Assignee: XILINX, INC.
    Inventors: Abhishek Joshi, Grigor S. Gasparyan
  • Patent number: 10963613
    Abstract: Partial reconfiguration of a programmable integrated circuit can include loading, using computer hardware, a platform design including a module black-box instance corresponding to a user design and marking, using the computer hardware, data of the platform design including data relating to synchronous boundary crossings between the platform design and the module black-box instance and implementation data for the platform design within an extended routing region available for routing the user design. Unmarked data can be removed from the platform design resulting in a shell circuit design. The user design can be implemented based on the shell circuit design and timing constraints corresponding to the marked data in the shell circuit design.
    Type: Grant
    Filed: July 26, 2019
    Date of Patent: March 30, 2021
    Assignee: Xilinx, Inc.
    Inventors: Meiwei Wu, Jun Liu, Raymond Kong
  • Patent number: 10956638
    Abstract: Methods and apparatus are described for providing and using programmable ICs suitable for meeting the unique desires of large hardware emulation systems. One example method of classifying a programmable IC having impaired circuitry generally includes determining a partitioning of programmable logic resources into two or more groups for classifying the programmable IC, testing the programmable IC to determine at least one location of the impaired circuitry in the programmable logic resources of the programmable IC, and classifying the programmable IC based on the at least one location of the impaired circuitry in relation to the partitioning of the programmable logic resources.
    Type: Grant
    Filed: July 17, 2019
    Date of Patent: March 23, 2021
    Assignee: XILINX, INC.
    Inventors: Bart Reynolds, Xiaojian Yang, Matthew H. Klein
  • Patent number: 10956241
    Abstract: A computer program product can include a non-transitory computer readable storage medium storing a unified container. The unified container can include a header structure, wherein the header structure has a fixed length and specifies a number of section headers included in the unified container. The unified container can include a plurality of section headers equivalent to the number of section headers specified in the header structure. The unified container can include a plurality of data sections corresponding to the plurality of section headers on a one-to-one basis. The plurality of data sections includes a first data section including a hardware binary and a second data section including a software binary. The hardware binary and the software binary are configured to program a programmable integrated circuit. Each section header specifies a type of data stored in the corresponding data section and specifies a mapping for the corresponding data section.
    Type: Grant
    Filed: December 20, 2017
    Date of Patent: March 23, 2021
    Assignee: Xilinx, Inc.
    Inventors: Hem C. Neema, Sonal Santan, Soren T. Soe, Stephen P. Rozum, Nik Cimino
  • Patent number: 10958067
    Abstract: An integrated circuit (IC) chip having circuitry adapted to detect and unlatch a latched transistor, and methods for operating the same are provided. In one example, an IC chip includes a body, a power rail disposed in the body and coupled to at least one of a plurality of contact pads disposed on the body, and a first core circuit disposed in the body. The first core circuit includes a first current limiting circuit, a silicon controlled rectifier (SCR) device having a first transistor, a second transistor, and a first latch sensing circuit. The first current limiting circuit is coupled to the power rail. First terminals of the first and second transistors are coupled to the first current limiting circuit. The first latch sensing circuit has a first input terminal coupled to second terminals of the first and second transistors. The first latch sensing circuit also has an output terminal coupled to the first current limiting circuit.
    Type: Grant
    Filed: September 19, 2018
    Date of Patent: March 23, 2021
    Assignee: XILINX, INC.
    Inventors: Pierre Maillard, Yanran Chen, Michael J. Hart
  • Publication number: 20210081215
    Abstract: Tracing status of a programmable device can include, in response to loading a device image for the programmable device, determining, using a processing unit on the programmable device, trace data for the device image, storing, by the processing unit, the trace data for the device image in a memory, and, in response to unloading the device image, recording the unloading of the device image in the trace data in the memory.
    Type: Application
    Filed: September 18, 2019
    Publication date: March 18, 2021
    Applicant: Xilinx, Inc.
    Inventors: David P. Schultz, Adrian M. Hernandez, David Robinson, Elessar Taggart, Max Heimer