Patents Assigned to Xilinx, Inc.
  • Patent number: 12261603
    Abstract: A System-on-Chip includes a data processing engine array. The data processing engine array includes a plurality of data processing engines organized in a grid. The plurality of data processing engines are partitioned into at least a first partition and a second partition. The first partition includes one or more first data processing engines of the plurality of data processing engines. The second partition includes one or more second data processing engines of the plurality of data processing engines. Each partition is configured to implement an application that executes independently of the other partition.
    Type: Grant
    Filed: May 18, 2023
    Date of Patent: March 25, 2025
    Assignee: Xilinx, Inc.
    Inventors: Sagheer Ahmad, Jaideep Dastidar, Brian C. Gaide, Juan J. Noguera Serra, Ian A. Swarbrick
  • Patent number: 12259833
    Abstract: Descriptor fetch for a direct memory access system includes obtaining a descriptor for processing a received data packet. A determination is made as to whether the descriptor is a head descriptor of a chain descriptor. In response to determining that the descriptor is a head descriptor, one or more tail descriptors are fetched from a descriptor table specified by the head descriptor. A number of the tail descriptors fetched is determined based on a running count of a buffer size of the chain descriptor determined as each tail descriptor is fetched compared to a size of the data packet.
    Type: Grant
    Filed: March 28, 2023
    Date of Patent: March 25, 2025
    Assignee: XILINX, INC.
    Inventors: Chandrasekhar S. Thyamagondlu, Tao Yu, Chiranjeevi Sirandas, Nicholas Trank
  • Publication number: 20250096136
    Abstract: A disclosed semiconductor device includes (1) a silicon stack comprising a front-side Back-End-of-Line (BEOL) stack and a back side BEOL stack, the front-side BEOL stack comprising a plurality of signal routes and the back-side BEOL stack comprising a plurality of power delivery routes, and (2) a plurality of auxiliary power paths formed within the front-side BEOL stack and electrically coupled to the plurality of power delivery routes of the back-side BEOL stack via a plurality of programmable switches, the plurality of power delivery routes, the plurality of programmable switches, and the plurality of auxiliary power paths forming a programmable power delivery network (PDN). Various other apparatuses, systems, and methods of operation are also disclosed.
    Type: Application
    Filed: September 20, 2023
    Publication date: March 20, 2025
    Applicants: Advanced Micro Devices, Inc., Xilinx, Inc.
    Inventors: Divya Madapusi Srinivas Prasad, Gabriel H. Loh, Richard Schultz, Jeffrey Richard Rearick, Shidhartha Das, Suresh Ramalingam
  • Patent number: 12254253
    Abstract: Resource estimation for implementing circuit designs in an integrated circuit (IC) can include detecting, using computer hardware, a plurality of Intellectual Property (IP) cores within a circuit design, extracting, using the computer hardware and from the circuit design, parameterizations for the plurality of IP cores as used in the circuit design, and selecting, using the computer hardware, a machine learning (ML) model corresponding to each IP core, wherein each selected ML model is specific to the corresponding IP core. Each selected ML model can be provided input specifying a target IC for the circuit design and the parameterization for the corresponding IP core. An estimate of resource usage for the circuit design can be generated by executing the selected ML models. The resource usage specifies an amount of resources of the target IC needed to implement the circuit design in the target IC.
    Type: Grant
    Filed: November 5, 2021
    Date of Patent: March 18, 2025
    Assignee: Xilinx, Inc.
    Inventors: Suman Kumar Timmireddy, Jaipal Reddy Nareddy, Rahul Kunwar, Adithya Balaji Boda
  • Publication number: 20250086007
    Abstract: Scheduling kernels on a system with heterogeneous compute circuits includes receiving, by a hardware processor, a plurality of kernels and a graph including a plurality of nodes corresponding to the plurality of kernels. The graph defines a control flow and a data flow for the plurality of kernels. The kernels are implemented within different ones of a plurality of compute circuits coupled to the hardware processor. A set of buffers for performing a job for the graph are allocated based, at least in part, on the data flow specified by the graph. Different ones of the kernels as implemented in the compute circuits are invoked based on the control flow defined by the graph.
    Type: Application
    Filed: September 11, 2023
    Publication date: March 13, 2025
    Applicant: Xilinx, Inc.
    Inventors: Sumit Nagpal, Abid Karumannil
  • Patent number: 12248761
    Abstract: Embodiments herein describe a solution for deterministic de-assertion of write and read resets of an asynchronous gearbox FIFO having unequal write and read data bit widths. Proposed approaches look for a stable region between read and write clock phases by sweeping one of the clock phases until the leading edges (phases) of both clocks are aligned then releasing the write and read resets deterministically based upon a change in cyclic behavior of detected logic levels of a reset beacon waveform.
    Type: Grant
    Filed: March 31, 2023
    Date of Patent: March 11, 2025
    Assignee: XILINX, INC.
    Inventors: Riyas Noorudeen Remla, Warren E. Cory
  • Patent number: 12248786
    Abstract: Controlling a data processing (DP) array includes creating a replica of a register address space of the DP array based on the design and the DP array. A sequence of instructions, including write instructions and read instructions, is received. The write instructions correspond to buffer descriptors specifying runtime data movements for a design for a DP array. The write instructions are converted into transaction instructions and the read instructions are converted into wait instructions based on the replica of the register address space. The transaction instructions and the wait instructions are included in an instruction buffer. The instruction buffer is provided to a microcontroller configured to execute the transaction instructions and the wait instructions to implement the runtime data movements for the design as implemented in the DP array. In another aspect, the instruction buffer is stored in a file for subsequent execution by the microcontroller.
    Type: Grant
    Filed: August 8, 2022
    Date of Patent: March 11, 2025
    Assignee: Xilinx, Inc.
    Inventors: Xiao Teng, Tejus Siddagangaiah, Bryan Lozano, Ehsan Ghasemi, Rajeev Patwari, Elliott Delaye, Jorn Tuyls, Aaron Ng, Sanket Pandit, Pramod Peethambaran, Satyaprakash Pareek
  • Publication number: 20250077760
    Abstract: Control set optimization for a circuit design includes generating, by a processor, Observability Don't Care (ODC) expressions for registers of the circuit design. Redundant reset pins of the registers of the circuit design are determined by the processor by iteratively checking, on a per-cube and a per-literal basis for each ODC expression, whether a value of a literal causes the ODC expression to evaluate to 1. A modified version of the circuit design is generated by the processor by connecting one or more reset pins of the set of redundant reset pins to one or more constants.
    Type: Application
    Filed: September 6, 2023
    Publication date: March 6, 2025
    Applicant: Xilinx, Inc.
    Inventors: Sandip Maity, Chun Zhang, Aman Gayasen
  • Publication number: 20250077757
    Abstract: Generating low skew clock solutions for local clocks in an integrated circuit includes, for a circuit design, determining a plurality of delay ranges for respective clock pins of a local clock net. Each delay range of the plurality of delay ranges includes an upper bound delay and a lower bound delay. The upper bound delays of the plurality of delay ranges are allocated as setup constraints for the respective clock pins of the local clock net. The lower bound delays are allocated as hold constraints for the respective clock pins of the local clock net. The local clock net is routed using the setup constraints and the hold constraints.
    Type: Application
    Filed: August 30, 2023
    Publication date: March 6, 2025
    Applicant: Xilinx, Inc.
    Inventor: Satish B. Sivaswamy
  • Patent number: 12244518
    Abstract: An integrated circuit (IC) includes a Network-on-Chip (NoC). The NoC includes a plurality of NoC master circuits, a plurality of NoC slave circuits, and a plurality of switches. The plurality of switches are interconnected and communicatively link the plurality of NoC master circuits with the plurality of NoC slave circuits. The plurality of switches are configured to receive data of different widths during operation and implement different operating modes for forwarding the data based on the different widths.
    Type: Grant
    Filed: May 13, 2022
    Date of Patent: March 4, 2025
    Assignee: Xilinx, Inc.
    Inventors: Krishnan Srinivasan, Sagheer Ahmad, Ygal Arbel, Aman Gupta
  • Patent number: 12235782
    Abstract: Embodiments herein describe a multi-chip device that includes multiple ICs with interconnected NoCs. Embodiments herein provided address translation circuitry in the ICs. The address translation circuitry establish a hierarchy where traffic originating for a first IC that is intended for a destination on a second IC is first routed to the address translation circuitry on the second IC which then performs an address translation and inserts the traffic back on the NoC in the second IC but with a destination ID corresponding to the destination. In this manner, the IC can have additional address apertures only to route traffic to the address translation circuitry of the other ICs rather than having address apertures for every destination in the other ICs.
    Type: Grant
    Filed: December 21, 2022
    Date of Patent: February 25, 2025
    Assignee: XILINX, INC.
    Inventors: Aman Gupta, Krishnan Srinivasan, Ahmad R. Ansari, Sagheer Ahmad
  • Patent number: 12237287
    Abstract: Embodiments herein describe a multiple die system that includes an interposer that connects a first die to a second die. Each die has a bump interface structure that is connected to the other structure using traces in the interposer. However, the bump interface structures may have different orientations relative to each other, or one of the interface structures defines fewer signals than the other. Directly connecting the corresponding signals defined by the structures to each other may be impossible to do in the interposer, or make the interposer too costly. Instead, the embodiments here simplify routing in the interposer by connecting the signals in the bump interface structures in a way that simplifies the routing but jumbles the signals. The jumbled signals can then be corrected using reordering circuitry in the dies (e.g., in the link layer and physical layer).
    Type: Grant
    Filed: September 15, 2023
    Date of Patent: February 25, 2025
    Assignee: XILINX, INC.
    Inventors: Ygal Arbel, Kenneth Ma, Balakrishna Jayadev, Sagheer Ahmad
  • Patent number: 12237829
    Abstract: An electronic system includes a source follower circuitry that functions as an input driver. The source follower circuitry includes a first input transistor, first current source circuitry, and first phase shift circuitry. The first input transistor includes a first node coupled to a first voltage node, a second node coupled to a first output node, and a gate node coupled to a first input node. The gate node receives a first input signal via the first input node. The first current source circuitry coupled to the first output node and configured to generate a first bias current. The first phase shift circuitry is coupled to the first current source circuitry. The first phase shift circuitry generates a first phase shift signal to modulate the first current source circuitry to reduce signal drop across the first input transistor.
    Type: Grant
    Filed: December 21, 2022
    Date of Patent: February 25, 2025
    Assignee: XILINX, INC.
    Inventors: Abhirup Lahiri, Christophe Erdmann
  • Patent number: 12235671
    Abstract: An integrated circuit (IC) device includes a circuit comprising pipeline stages, and a controller circuitry configured to: load a static value into each of the pipeline stages based on a change in a clock enable (CE) signal, and sequentially deactivate each of the pipeline stages after a quantity of cycles of a reference clock signal that occur after the change of the CE signal, wherein the quantity of the cycles of the clock signal is based on a quantity of the pipeline stages.
    Type: Grant
    Filed: May 19, 2023
    Date of Patent: February 25, 2025
    Assignee: XILINX, INC.
    Inventor: Brian C. Gaide
  • Patent number: 12235950
    Abstract: Embodiments herein describe partitioning hardware and software in a system on a chip (SoC) into a hierarchy. In one embodiment, the hierarchy includes three levels of hardware-software configurations, enabling security and/or safety isolation across those three levels. The levels can cover the processor subsystem with compute, memory, acceleration, and peripheral resources shared or divided across those three levels.
    Type: Grant
    Filed: January 18, 2022
    Date of Patent: February 25, 2025
    Assignee: XILINX, INC.
    Inventors: Jaideep Dastidar, James Murray, Stefano Stabellini
  • Patent number: 12231532
    Abstract: Examples herein describe a scalable tweak engine and prefetching tweak values. Regarding the scalable tweak engine, it can be designed to accommodate different bus widths of data. The scalable tweak engine described herein includes multiple tweak calculators that can be daisy chained together to output multiple tweak values every clock cycle. These tweak values can be sent to multiple encryption cores so that multiple data blocks can be encrypted in parallel. Regarding prefetching tweak values, previous encryption engines incur a delay as the tweak value (e.g., a metadata value) for a data block is calculated. In the embodiments herein, the encryption engine can include an independent metadata engine that determines the metadata value for a subsequent data block while the current data block is being encrypted.
    Type: Grant
    Filed: March 26, 2020
    Date of Patent: February 18, 2025
    Assignee: XILINX, INC.
    Inventors: Devanjan Maiti, Robert Bellarmin Susai, Jayaram Pvss
  • Patent number: 12223355
    Abstract: Synchronizing system resources of a multi-socket data processing system can include providing, from a primary System-on-Chip (SOC), a trigger event to a global synchronization circuit. The primary SOC is one of a plurality of SOCS and the trigger event is provided over a first sideband channel. In response to the trigger event, the global synchronization circuit is capable of broadcasting a synchronization event to the plurality of SOCS over a second sideband channel. In response to the synchronization event, the system resource of each SOC of the plurality of SOCS is programmed with a common value. The programming synchronizes the system resources of the plurality of SOCS.
    Type: Grant
    Filed: November 16, 2021
    Date of Patent: February 11, 2025
    Assignee: Xilinx, Inc.
    Inventors: Karthik Shankar, Jaideep Dastidar, Ahmad R. Ansari, Sagheer Ahmad
  • Patent number: 12224954
    Abstract: A network interface device has an interface configured to interface with a network. The interface is configured to at least one of receive data from the network and put data onto the network. The network interface device has an application specific integrated device with a plurality of data processing pipelines to process at least one of data which has been received from the network and data which is to be put onto said network and an FPGA arranged in a path parallel to the data processing pipelines.
    Type: Grant
    Filed: October 29, 2021
    Date of Patent: February 11, 2025
    Assignee: XILINX, INC.
    Inventors: Steven L. Pope, Dmitri Kitariev, Derek Roberts
  • Publication number: 20250044827
    Abstract: A system for clock variation measurement includes a first clock counter circuit configured to generate a plurality of first counts of a first clock signal, a second clock counter circuit configured to generate a plurality of second counts of a second clock signal, a first synchronizer circuit configured to synchronize the plurality of first counts according to a third clock signal, and a second synchronizer circuit configured to synchronize the plurality of second counts according to the third clock signal. The system includes a difference circuit configured to generate a plurality of differences from respective count pairs as synchronized. The system includes a variation circuit configured to generate a variation signal indicating an amount of variation between the first clock signal and the second clock signal based, at least in part, on the plurality of differences.
    Type: Application
    Filed: August 2, 2023
    Publication date: February 6, 2025
    Applicant: Xilinx, Inc.
    Inventor: Riyas Noorudeen Remla
  • Publication number: 20250036848
    Abstract: A method for predicting voltage drop on a power delivery network of a 3D stacked device includes receiving a spatial power distribution map of a plurality of semiconductor dies of the 3D stacked device, receiving a spatial power source node location map for a plurality of power source nodes coupled to the 3D stacked device, dividing vertically the spatial power distribution map and the spatial power source node location map into overlapping windows, determining a voltage drop map in each of the windows based on the divided spatial power distribution map and the divided spatial power source node location map, and combining the voltage drop map in each of the windows to form a composite voltage drop map.
    Type: Application
    Filed: July 27, 2023
    Publication date: January 30, 2025
    Applicant: XILINX, INC.
    Inventors: Aashish TRIPATHI, Sundeep Ram Gopal AGARWAL, Ashit DEBNATH, Atreyee SAHA, Praful JAIN