Abstract: Controlling a data processing (DP) array includes creating a replica of a register address space of the DP array based on the design and the DP array. A sequence of instructions, including write instructions and read instructions, is received. The write instructions correspond to buffer descriptors specifying runtime data movements for a design for a DP array. The write instructions are converted into transaction instructions and the read instructions are converted into wait instructions based on the replica of the register address space. The transaction instructions and the wait instructions are included in an instruction buffer. The instruction buffer is provided to a microcontroller configured to execute the transaction instructions and the wait instructions to implement the runtime data movements for the design as implemented in the DP array. In another aspect, the instruction buffer is stored in a file for subsequent execution by the microcontroller.

Abstract: Generating low skew clock solutions for local clocks in an integrated circuit includes, for a circuit design, determining a plurality of delay ranges for respective clock pins of a local clock net. Each delay range of the plurality of delay ranges includes an upper bound delay and a lower bound delay. The upper bound delays of the plurality of delay ranges are allocated as setup constraints for the respective clock pins of the local clock net. The lower bound delays are allocated as hold constraints for the respective clock pins of the local clock net. The local clock net is routed using the setup constraints and the hold constraints.

Abstract: Control set optimization for a circuit design includes generating, by a processor, Observability Don't Care (ODC) expressions for registers of the circuit design. Redundant reset pins of the registers of the circuit design are determined by the processor by iteratively checking, on a per-cube and a per-literal basis for each ODC expression, whether a value of a literal causes the ODC expression to evaluate to 1. A modified version of the circuit design is generated by the processor by connecting one or more reset pins of the set of redundant reset pins to one or more constants.

Abstract: An integrated circuit (IC) includes a Network-on-Chip (NoC). The NoC includes a plurality of NoC master circuits, a plurality of NoC slave circuits, and a plurality of switches. The plurality of switches are interconnected and communicatively link the plurality of NoC master circuits with the plurality of NoC slave circuits. The plurality of switches are configured to receive data of different widths during operation and implement different operating modes for forwarding the data based on the different widths.

Abstract: Embodiments herein describe partitioning hardware and software in a system on a chip (SoC) into a hierarchy. In one embodiment, the hierarchy includes three levels of hardware-software configurations, enabling security and/or safety isolation across those three levels. The levels can cover the processor subsystem with compute, memory, acceleration, and peripheral resources shared or divided across those three levels.

Abstract: Embodiments herein describe a multiple die system that includes an interposer that connects a first die to a second die. Each die has a bump interface structure that is connected to the other structure using traces in the interposer. However, the bump interface structures may have different orientations relative to each other, or one of the interface structures defines fewer signals than the other. Directly connecting the corresponding signals defined by the structures to each other may be impossible to do in the interposer, or make the interposer too costly. Instead, the embodiments here simplify routing in the interposer by connecting the signals in the bump interface structures in a way that simplifies the routing but jumbles the signals. The jumbled signals can then be corrected using reordering circuitry in the dies (e.g., in the link layer and physical layer).

Abstract: An electronic system includes a source follower circuitry that functions as an input driver. The source follower circuitry includes a first input transistor, first current source circuitry, and first phase shift circuitry. The first input transistor includes a first node coupled to a first voltage node, a second node coupled to a first output node, and a gate node coupled to a first input node. The gate node receives a first input signal via the first input node. The first current source circuitry coupled to the first output node and configured to generate a first bias current. The first phase shift circuitry is coupled to the first current source circuitry. The first phase shift circuitry generates a first phase shift signal to modulate the first current source circuitry to reduce signal drop across the first input transistor.

Abstract: Embodiments herein describe a multi-chip device that includes multiple ICs with interconnected NoCs. Embodiments herein provided address translation circuitry in the ICs. The address translation circuitry establish a hierarchy where traffic originating for a first IC that is intended for a destination on a second IC is first routed to the address translation circuitry on the second IC which then performs an address translation and inserts the traffic back on the NoC in the second IC but with a destination ID corresponding to the destination. In this manner, the IC can have additional address apertures only to route traffic to the address translation circuitry of the other ICs rather than having address apertures for every destination in the other ICs.

Abstract: An integrated circuit (IC) device includes a circuit comprising pipeline stages, and a controller circuitry configured to: load a static value into each of the pipeline stages based on a change in a clock enable (CE) signal, and sequentially deactivate each of the pipeline stages after a quantity of cycles of a reference clock signal that occur after the change of the CE signal, wherein the quantity of the cycles of the clock signal is based on a quantity of the pipeline stages.

Abstract: Examples herein describe a scalable tweak engine and prefetching tweak values. Regarding the scalable tweak engine, it can be designed to accommodate different bus widths of data. The scalable tweak engine described herein includes multiple tweak calculators that can be daisy chained together to output multiple tweak values every clock cycle. These tweak values can be sent to multiple encryption cores so that multiple data blocks can be encrypted in parallel. Regarding prefetching tweak values, previous encryption engines incur a delay as the tweak value (e.g., a metadata value) for a data block is calculated. In the embodiments herein, the encryption engine can include an independent metadata engine that determines the metadata value for a subsequent data block while the current data block is being encrypted.

Abstract: A network interface device has an interface configured to interface with a network. The interface is configured to at least one of receive data from the network and put data onto the network. The network interface device has an application specific integrated device with a plurality of data processing pipelines to process at least one of data which has been received from the network and data which is to be put onto said network and an FPGA arranged in a path parallel to the data processing pipelines.

Abstract: Synchronizing system resources of a multi-socket data processing system can include providing, from a primary System-on-Chip (SOC), a trigger event to a global synchronization circuit. The primary SOC is one of a plurality of SOCS and the trigger event is provided over a first sideband channel. In response to the trigger event, the global synchronization circuit is capable of broadcasting a synchronization event to the plurality of SOCS over a second sideband channel. In response to the synchronization event, the system resource of each SOC of the plurality of SOCS is programmed with a common value. The programming synchronizes the system resources of the plurality of SOCS.

Abstract: A system for clock variation measurement includes a first clock counter circuit configured to generate a plurality of first counts of a first clock signal, a second clock counter circuit configured to generate a plurality of second counts of a second clock signal, a first synchronizer circuit configured to synchronize the plurality of first counts according to a third clock signal, and a second synchronizer circuit configured to synchronize the plurality of second counts according to the third clock signal. The system includes a difference circuit configured to generate a plurality of differences from respective count pairs as synchronized. The system includes a variation circuit configured to generate a variation signal indicating an amount of variation between the first clock signal and the second clock signal based, at least in part, on the plurality of differences.

Abstract: A method for predicting voltage drop on a power delivery network of a 3D stacked device includes receiving a spatial power distribution map of a plurality of semiconductor dies of the 3D stacked device, receiving a spatial power source node location map for a plurality of power source nodes coupled to the 3D stacked device, dividing vertically the spatial power distribution map and the spatial power source node location map into overlapping windows, determining a voltage drop map in each of the windows based on the divided spatial power distribution map and the divided spatial power source node location map, and combining the voltage drop map in each of the windows to form a composite voltage drop map.

Abstract: An integrated circuit (IC) device includes an error correction code (ECC) encoder circuitry configured to receive input data, determine min-terms in a Hamming matrix (H-Matrix) corresponding to the input data, and generate ECC data based on the min-terms and an output codeword based on the ECC data, and an error correction circuitry configured to generate a corrected output codeword based on the output codeword.

Abstract: Remote kernel execution in a heterogeneous computing system can include executing, using a device processor of a device communicatively linked to a host processor, a device runtime and receiving from the host processor within a hardware submission queue of the device, a command. The command requests execution of a software kernel and specifies a descriptor stored in a region of a memory of the device shared with the host processor. In response to receiving the command, the device runtime, as executed by the device processor, invokes a runner program associated with the software kernel. The runner program can map a physical address of the descriptor to a virtual memory address corresponding to the descriptor that is usable by the software kernel. The runner program can execute the software kernel. The software kernel can access data specified by the descriptor using the virtual memory address as provided by the runner program.

Abstract: A computing node for a computing system includes a processor, conversion circuitry, and routing circuitry. The processor generates a data signal based on a function of an application executed by the computing system. The data signal has a first precision format and a first sparse representation. The conversion circuitry receives the data signal from the processor and generate a converted data signal by at least one of converting the first precision format to a second precision format and converting the first sparse representation to a second sparse representation. The routing circuitry transmits the converted data signal to switch circuitry of the computing system.

Abstract: Methods and apparatus for calibrating a gain for a circuit block are disclosed. An example method includes receiving a plurality of quantizer offsets, where the plurality of quantizer offsets represent calibration data for a quantizer configured to quantize an output of the circuit block, determining one or more differences based on one or more first quantizer offsets of the plurality of quantizer offsets and on one or more second quantizer offsets of the plurality of quantizer offsets, and determining an incremental change in a gain associated with the circuit block based on the one or more differences.

Abstract: A communication system includes link circuits that receive serial data over one or more input serial links. The link circuits include a primary link circuit and a secondary link circuit. The secondary link circuit includes a de-serializer circuit configured to receive the serial data from the one or more input serial links and convert the serial data into parallel data, and an aligner circuit comprising a memory. The aligner circuit stops at least one of storing the parallel data in the memory and reading the memory based on a channel bonding signal generated based on a channel bonding symbol within the serial data. The aligner circuit outputs the channel bonding signal to a finite state machine (FSM) circuit of the primary link circuit. The aligner circuit outputs the parallel data based on receiving a read signal from the FSM circuit of the primary link circuit.

Abstract: An integrated circuitry (IC) device for a memory device includes driver circuitry, selection circuitry, clock generation circuitry, and self-time path circuitry. The driver circuitry generates a plurality of driver circuitry outputs. The selection circuitry selects one of the plurality of driver circuitry outputs based on a plurality of enable signals. The clock generation circuitry receives the selected one of the plurality of driver circuitry outputs from the selection circuitry, and generates a clock signal based on at least the selected one of the plurality of driver circuitry outputs from the selection circuitry. The self-time path circuitry of a memory receives the clock signal and generates a reset signal based on the clock signal. The plurality of driver circuitry outputs and the clock signal are based on the reset signal, and the self-time path circuitry corresponds to one or more columns of a memory bank.