Patents Assigned to Xilinx, Inc.
  • Publication number: 20210042252
    Abstract: A device includes a platform implemented, at least in part, in a static region of programmable circuitry and a dynamic region of programmable circuitry configured to implement user-specified circuitry in communication with the platform. The platform is configured to establish and maintain a first communication link with a host data processing system and a second communication link with a network while at least a portion of the dynamic region of programmable circuitry is dynamically reconfigured.
    Type: Application
    Filed: August 11, 2019
    Publication date: February 11, 2021
    Applicant: Xilinx, Inc.
    Inventors: Chandrasekhar S. Thyamagondlu, Ravi Sunkavalli, Ravi N. Kurlagunda, Ellery Cochell
  • Patent number: 10917077
    Abstract: A device includes a plurality of phase accumulators, a multiplexer, and an oscillator. The plurality of phase accumulators is configured to receive a plurality of frequencies and generate a plurality of ramp signals. The multiplexer is configured to receive the plurality of ramp signals from the plurality of phase accumulators and to select one ramp signal from the plurality of ramp signals. The oscillator is configured to receive the one selected ramp signal and to generate one amplitude signal associated therewith. The plurality of phase accumulators continues generating their respective ramp signal. The multiplexer subsequent to selecting the one ramp signal is configured to select another ramp signal associated with another one phase accumulator of the plurality of phase accumulators. The oscillator is further configured to receive the selected another ramp signal and to generate another amplitude signal associated therewith.
    Type: Grant
    Filed: November 25, 2019
    Date of Patent: February 9, 2021
    Assignee: XILINX, INC.
    Inventors: Ali Boumaalif, John E. McGrath
  • Patent number: 10916516
    Abstract: Methods and apparatus are described for adding one or more features (e.g., high bandwidth memory (HBM)) to a qualified stacked silicon interconnect (SSI) technology programmable integrated circuit (IC) region by providing an interface (e.g., an HBM buffer region implemented with a hierarchical switch network) between the added feature device and the programmable IC region. One example apparatus generally includes a programmable IC region and an interface region configured to couple the programmable IC region to at least one fixed feature die via a first plurality of ports associated with the at least one fixed feature die and a second plurality of ports associated with the programmable IC region. The interface region is configured as a switch network between the first plurality of ports and the second plurality of ports, and the switch network includes a plurality of full crossbar switch networks.
    Type: Grant
    Filed: June 7, 2017
    Date of Patent: February 9, 2021
    Assignee: XILINX, INC.
    Inventors: Martin Newman, Sagheer Ahmad
  • Patent number: 10911060
    Abstract: Apparatus and associated methods relate to a time-interleaved integrating sampling front-end circuit using integrating buffers. In an illustrative example, a circuit may include N sampling layers of circuits, an ith sampling layer of circuits of the N sampling layers of circuits may include: (a) Xi buffers configured to receive an analog signal, Xi?1, and, (b) Yi track-and-hold circuits, each track-and-hold circuit of the Yi track-and-hold circuits is coupled to an output of a corresponding buffer of the X buffers, Yi?1, at least one buffer of the Xi buffers may include an integrating buffer, N?i?1. By implementing integrating buffers, a faster linear type of step settling response may be obtained as opposed to a slower exponential type of settling response.
    Type: Grant
    Filed: November 14, 2019
    Date of Patent: February 2, 2021
    Assignee: XILINX, INC.
    Inventors: Pedro W. Neto, Ronan Casey, Declan Carey
  • Patent number: 10909292
    Abstract: In an example, a configurable block for a programmable device of a plurality of programmable devices in an integrated circuit (IC) includes a first flip-flop having a data port coupled to an output of an interface block of the programmable device, a clock port coupled to a first clock input, and an output port coupled to a first output. The configurable block further includes a second flip-flop having a data port coupled to the output of the interface block, a clock port coupled to the first clock input, and an output port coupled to a second output, and a first multiplexer having a first input port coupled to the output port of the first flip-flop, and a second input port coupled to the output port of the second flip-flop. The configurable block further includes a third flip-flop having an input port coupled to an output of the first multiplexer, a clock port coupled to a second clock input, and an output port coupled to a third output.
    Type: Grant
    Filed: February 14, 2019
    Date of Patent: February 2, 2021
    Assignee: XILINX, INC.
    Inventor: Pongstorn Maidee
  • Patent number: 10908598
    Abstract: Examples described herein provide a method for designing an integrated circuit (IC) for meeting different sets of criteria. In an example, different sets of criteria are identified for an IC design. The IC design is designed to meet the different sets of criteria based on expected manufacturing variation. The IC design is caused to be manufactured as IC products. At least some of the IC products are caused to be tested. The IC products are characterized as meeting respective ones of the different sets of criteria based on testing the at least some of the IC products.
    Type: Grant
    Filed: May 30, 2019
    Date of Patent: February 2, 2021
    Assignee: XILINX, INC.
    Inventor: Praful Jain
  • Publication number: 20210026689
    Abstract: A network interface device has an input configured to receive data from a network. The data is for one of a plurality of different applications. The network interface device also has at least one processor configured to determine which of a plurality of available different caches in a host system the data is to be injected by accessing to a receive queue comprising at least one descriptor indicating a cache location in one of said plurality of caches to which data is to be injected, wherein said at least one descriptor, which indicates the cache location, has an effect on subsequent descriptors of said receive queue until a next descriptor indicates another cache location. The at least one processor is also configured to cause the data to be injected to the cache location in the host system.
    Type: Application
    Filed: October 13, 2020
    Publication date: January 28, 2021
    Applicant: Xilinx, Inc.
    Inventors: Steven Leslie Pope, David James Riddoch
  • Patent number: 10901097
    Abstract: An electronics-harmful-radiation (EHR) monitoring system includes an EHR measurement circuit. The EHR measurement circuit includes a first device, a single event upset (SEU) detector circuit configured to determine a first number of SEUs of the first device during a first period, and an EHR measurement generator configured to generate a first EHR value based on the first number of SEUs and the first period.
    Type: Grant
    Filed: March 5, 2018
    Date of Patent: January 26, 2021
    Assignee: Xilinx, Inc.
    Inventors: James Karp, Michael J. Hart
  • Patent number: 10902315
    Abstract: The present disclosure relates to a processor for implementing artificial neural networks, for example, convolutional neural networks. The processor includes a memory controller group, an on-chip bus and a processor core, wherein the processor core further includes a register map, an instruction module, a data transferring controller, a data writing scheduling unit, a buffer module, a convolution operation unit and a hybrid computation unit. The processor of the present disclosure may be used for implementing various neural networks with increased computation efficiency.
    Type: Grant
    Filed: May 22, 2017
    Date of Patent: January 26, 2021
    Assignee: XILINX, INC.
    Inventors: Shaoxia Fang, Lingzhi Sui, Qian Yu, Junbin Wang, Yi Shan
  • Patent number: 10896119
    Abstract: An input-output circuit is coupled to a plurality of serial communication paths and to a physical point-to-point interface. The input-output circuit is configured to transmit data received on the plurality of serial communication paths over the physical point-to-point interface. An application circuit is coupled to the input-output circuit and is configured to communicate via a first one of the paths in performing application functions. A bridge circuit is coupled to the input-output circuit and is configured to communicate via a second one of the paths. A debug circuit is coupled to the application circuit and to the bridge circuit. The debug circuit is configured to capture debug data of the application circuit and provide the debug data to the bridge circuit for communication via the second one of the paths.
    Type: Grant
    Filed: November 5, 2018
    Date of Patent: January 19, 2021
    Assignee: Xilinx, Inc.
    Inventors: Ahmad R. Ansari, Felix Burton, Henry C. Yu
  • Publication number: 20210014343
    Abstract: Data is received at a buffer used by a protocol processing stack which protocol processes the received data. The received data is made available to, for example, an application, before the protocol processing of the data is complete. If the protocol processing is successful, the data made available to the application is committed.
    Type: Application
    Filed: September 29, 2020
    Publication date: January 14, 2021
    Applicant: Xilinx, Inc.
    Inventors: Steve Pope, Kieran Mansley, Sian James, David J. Riddoch
  • Publication number: 20210011172
    Abstract: Systems and methods for monitoring a number of operating conditions of a programmable device are disclosed. In some implementations, the system may include a root monitor including circuitry configured to generate a reference voltage, a plurality of sensors and satellite monitors distributed across the programmable device, and a interconnect system coupled to the root monitor and to each of the plurality of satellite monitors. Each of the satellite monitors may be in a vicinity of and coupled to a corresponding one of the plurality of sensors via a local interconnect. The interconnect system may include one or more analog channels configured to distribute the reference voltage to each of the plurality of satellite monitors, and may include one or more digital channels configured to selectively route digital data from each of the plurality of satellite monitors to the root monitor as data packets.
    Type: Application
    Filed: July 9, 2019
    Publication date: January 14, 2021
    Applicant: Xilinx, Inc.
    Inventors: Brendan Farley, John K. Jennings, John G. O'Dwyer
  • Patent number: 10891414
    Abstract: For an application specifying a software portion for implementation within a data processing engine (DPE) array of a device and a hardware portion for implementation within programmable logic (PL) of the device, a logical architecture for the application and a first interface solution specifying a mapping of logical resources to hardware of an interface circuit block between the DPE array and the programmable logic are generated. A block diagram of the hardware portion is built based on the logical architecture and the first interface solution. An implementation flow is performed on the block diagram. The software portion of the application is compiled for implementation in one or more DPEs of the DPE array.
    Type: Grant
    Filed: May 23, 2019
    Date of Patent: January 12, 2021
    Assignee: Xilinx, Inc.
    Inventors: Shail Aditya Gupta, Srinivas Beeravolu, Dinesh K. Monga, Pradip Jha, Vishal Suthar, Vinod K. Kathail, Vidhumouli Hunsigida, Siddarth Rele
  • Patent number: 10891413
    Abstract: Disclosed approaches for processing a circuit design include providing access to checkpoint data of a design checkpoint of a circuit design and starting child processes by a parent process. An initial intermediate representation is generated by the parent process, and concurrent with the generating of the initial intermediate representation, the child processes load the checkpoint data into respective memory spaces. The parent process produces incremental updates to the design checkpoint. The parent process signals availability of the incremental updates to the child processes, which apply the incremental updates to the checkpoint data in the respective memory spaces. The child processes process the circuit design in response to completion of producing incremental updates by the parent placer process.
    Type: Grant
    Filed: December 5, 2019
    Date of Patent: January 12, 2021
    Assignee: Xilinx, Inc.
    Inventors: Paul D. Kundarewich, Grigor S. Gasparyan, Mehrdad Eslami Dehkordi, Guenter Stenz
  • Patent number: 10891132
    Abstract: For an application having a software portion for implementation in a data processing engine (DPE) array of a device and a hardware portion for implementation in programmable logic (PL) of the device, an implementation flow is performed, using a processor executing a hardware compiler, on the hardware portion based on an interface block solution that maps logical resources used by the software portion to hardware of an interface block coupling the DPE array to the PL. In response to not meeting a design metric during the implementation flow, an interface block constraint is provided from the hardware compiler to a DPE compiler. In response to receiving the interface block constraint, an updated interface block solution is generated, using the processor executing the DPE compiler, and provided from the DPE compiler to the hardware compiler.
    Type: Grant
    Filed: May 23, 2019
    Date of Patent: January 12, 2021
    Assignee: Xilinx, Inc.
    Inventors: Shail Aditya Gupta, Rishi Surendran
  • Patent number: 10893005
    Abstract: Examples described herein provide for an electronic circuit, such as a System-on-Chip (SoC), having a Network-on-Chip (NoC). The NoC is configurable and has capabilities to be partially reconfigured. In an example, a NoC on an integrated circuit is configured. Subsystems on the integrated circuit communicate via the NoC. The NoC is partially reconfigured. A first subset of the NoC is reconfigured during the partial reconfiguration, and a second subset of the NoC is capable of continuing to pass communications uninterruptedly during the partial reconfiguration. After the partial reconfiguration, two or more of the subsystems communicate via the first subset of the NoC.
    Type: Grant
    Filed: September 17, 2018
    Date of Patent: January 12, 2021
    Assignee: XILINX, INC.
    Inventors: David P. Schultz, Ian A. Swarbrick, Jun Liu, Raymond Kong, Herve Alexanian
  • Patent number: 10892918
    Abstract: A speculative decision feedback equalizer with split unroll multiplexers is provided. The speculative decision feedback equalizer splits an unroll multiplexer into two multiplexers. One split multiplexer provides a data path for the unroll selection signal, and the other split multiplexer provides a separate data path for the summer differential tap. In this way, the loading of an input stage of the summer circuit and the loading from the h1 unrolling loop are decoupled, allowing each split multiplexer to be configured according to a specific timing requirement along a respective data path. Thus, timing performance of the speculative decision feedback equalizer is improved.
    Type: Grant
    Filed: July 26, 2019
    Date of Patent: January 12, 2021
    Assignee: Xilinx, Inc.
    Inventors: Haritha Eachempatti, Hsung Jai Im
  • Patent number: 10886906
    Abstract: A duty-cycle adjustment circuit receives a differential pair of input signals and generates an output signal based on the differential pair. The duty-cycle adjustment circuit drives the output signal to a logic-high state based on transitions of a first polarity in a first input signal of the differential pair, and drives the output signal to a logic-low state based on transitions of the first polarity in a second input signal of the differential pair. For example, rising-edge transitions of the output signal may be aligned with rising-edge transitions of the first input signal, and falling-edge transitions of the output signal may be aligned with rising-edge transitions of the second input signal. Alternatively, rising-edge transitions of the output signal may be aligned with falling-edge transitions of the first input signal, and falling-edge transitions of the output signal may be aligned with falling-edge transitions of the second input signal.
    Type: Grant
    Filed: May 25, 2018
    Date of Patent: January 5, 2021
    Assignee: Xilinx, Inc.
    Inventors: Bob W. Verbruggen, Christophe Erdmann, Conrado K. Mesadri
  • Patent number: 10886921
    Abstract: Examples described herein generally relate to multi-chip devices having stacked chips. In an example, a multi-chip device includes a chip stack including a base chip and two or more overlying chips overlying the base chip. Neighboring chips of the chip stack are connected to each other. The chip stack includes identification generation connections and circuits configured to generate a unique identification of each overlying chip based on a relative position of the respective overlying chip with reference to the base chip. The chip stack includes a communication channel from the base chip to each overlying chip. Each overlying chip includes comparison and enable/disable logic (CEDL) communicatively coupled to the communication channel. The CEDL is configured to compare a target identification of data received by the respective overlying chip to the unique identification of the respective overlying chip and responsively enable or disable a recipient circuit of the respective overlying chip.
    Type: Grant
    Filed: March 20, 2020
    Date of Patent: January 5, 2021
    Assignee: XILINX, INC.
    Inventors: Vijay Kumar Koganti, Anil Kumar Kandala, Santosh Yachareni
  • Patent number: 10878150
    Abstract: Disclosed approaches for optimizing netlist loops include associating loop optimization methods with loop patterns in a computer memory. A circuit design can be synthesized into a netlist, and netlist loops that conform to the loop patterns can be identified. For each matching netlist loop, a loop optimization method associated with the loop pattern to which the netlist loop conforms can be selected. For each netlist loop, the loop optimization method associated with the loop pattern to which the netlist loop conforms can be performed to modify logic of the netlist loop in the netlist.
    Type: Grant
    Filed: September 17, 2019
    Date of Patent: December 29, 2020
    Assignee: Xilinx, Inc.
    Inventor: Hossein Omidian Savarbaghi