Patents Assigned to Xilinx, Inc.
  • Patent number: 10949586
    Abstract: Approaches for post-synthesis insertion of debug cores include a programmed processor inputting data that identify signals of a synthesized circuit design to be probed and determining whether or not debug cores and interfaces needed to probe the signals are absent from the circuit design. The programmed processor creates, in response to determining that the debug cores and interfaces are absent, the debug cores and interfaces in the circuit design. The programmed processor couples the debug cores and interfaces to the signals in the circuit design and synthesizes the debug cores and interfaces created in the circuit design to create a modified circuit design. The method includes generating a circuit definition from the modified circuit design by the programmed processor, and implementing a circuit that operates according to the circuit definition.
    Type: Grant
    Filed: July 1, 2020
    Date of Patent: March 16, 2021
    Assignee: XILINX, INC.
    Inventors: Jaipal R. Nareddy, Suman Kumar Timmireddy, Rahul Gupta
  • Patent number: 10949258
    Abstract: A device includes a first and a second stage round robin arbitrations receiving request signals associated with a first, a second and a third user. At least one request signal for each of the first, the second, and the third user is asserted to access a common resource. The first stage round robin arbitration selects the first, the second, and the third user in a round robin fashion, at a first, a second, and a third iteration. The second stage round robin arbitration receives the user selection and the plurality of request signals and at the first, the second, and the third iteration grants access to the common resource to one request signal associated with the first, the second, and the third user. At each subsequent iteration the first stage round robin arbitration selects a different user and grants access to another request signal until all request signals are processed.
    Type: Grant
    Filed: December 2, 2019
    Date of Patent: March 16, 2021
    Assignee: XILINX, INC.
    Inventors: Tejinder Kumar, Surender Kisanagar
  • Patent number: 10951249
    Abstract: A transmit circuit operated with time-interpolated digital pre-distortion (DPD) coefficients to improve adjacent channel power ratio (ACPR) performance during a power mode change is provided. The transmit circuit includes a DPD circuit configured to operate with a first DPD coefficient according to a first transmit power level of a transmit power amplifier of the transmit circuit. The transmit circuit further includes a DPD coefficient management engine configured to retrieve a second DPD coefficient corresponding to the second transmit power level. The transmit circuit further includes a DPD coefficient time-interpolation engine configured to compute a set of time-interpolated DPD coefficients corresponding to a set of time instants for a transient period when the transmit power amplifier is adapted to the second DPD coefficient.
    Type: Grant
    Filed: March 26, 2020
    Date of Patent: March 16, 2021
    Assignee: Xilinx, Inc.
    Inventors: Hongzhi Zhao, Vince C Barnes, Xiaohan Chen, Hemang Parekh
  • Patent number: 10944417
    Abstract: A DAC current steering circuit includes a first transistor whose: drain is coupled to a first output, source is coupled to a drain of a second transistor at a first node, and gate is coupled to a data input, and a third transistor whose: drain is coupled to a second output, source is coupled to a drain of a fourth transistor at a second node, and gate is coupled to a complement of the data input. The circuit further includes first and second shadow capacitors respectively coupled, via first and second switches, between the first and second nodes and ground, the first and second switches respectively controlled by the complement of the data input, and the data input.
    Type: Grant
    Filed: July 7, 2020
    Date of Patent: March 9, 2021
    Assignee: XILINX, INC.
    Inventor: Abhirup Lahiri
  • Patent number: 10944414
    Abstract: An apparatus and method for sampling an analog signal with analog-to-digital converters (ADCs) is disclosed. The ADCs may be separated into a group of interleaved ADCs and a spare ADC. The interleaved ADCs can sample the analog signal according to an interleaving sequence. An interleaved ADC controller can monitor the inactivity of the spare ADC and can replace one of the interleaved ADCs in the interleaving sequence with the spare ADC based on the inactivity.
    Type: Grant
    Filed: July 7, 2020
    Date of Patent: March 9, 2021
    Assignee: Xilinx, Inc.
    Inventors: Bruno Miguel Vaz, Bob W. Verbruggen, Christophe Erdmann
  • Patent number: 10943039
    Abstract: An example multiply accumulate (MACC) circuit includes: a multiply-accumulator having an accumulator output register; a quantizer, coupled to the multiply accumulator; and a control circuit coupled to the multiply-accumulator and the quantizer, the control circuit configured to provide control data to the quantizer, the control data indicative of a most-significant bit (MSB) to least significant bit (LSB) range for selecting bit indices from the accumulator output register.
    Type: Grant
    Filed: October 17, 2017
    Date of Patent: March 9, 2021
    Assignee: XILINX, INC.
    Inventors: Ashish Sirasao, Elliott Delaye, Sean Settle, Zhao Ma, Ehsan Ghasemi, Xiao Teng, Aaron Ng, Jindrich Zejda
  • Patent number: 10944444
    Abstract: A digital predistortion (DPD) system includes an input configured to receive a DPD input signal. In some embodiments, a non-linear datapath is coupled to the input, where the non-linear datapath includes a plurality of parallel datapath elements each coupled to the input. By way of example, each of the plurality of parallel datapath elements is configured to add a different inverse non-linear component to the DPD input signal corresponding to a non-linear component of an amplifier. In various examples, a first combiner combines an output of each of the plurality of datapath elements to generate a first predistortion signal. In some embodiments, the DPD system further includes a linear datapath coupled to the input in parallel with the non-linear datapath to generate a second predistortion signal. In addition, a second combiner combines the first predistortion signal and the second predistortion signal to generate a DPD output signal.
    Type: Grant
    Filed: September 26, 2018
    Date of Patent: March 9, 2021
    Assignee: Xilinx, Inc.
    Inventors: Christopher H. Dick, Hongzhi Zhao, Hemang M. Parekh, Xiaohan Chen
  • Patent number: 10943042
    Abstract: A computer-implemented method includes compiling a Register Transfer Level (RTL) code to form a data flow graph (DFG). The computer-implemented method includes identifying a chain of multiplexers in the DFG, wherein the chain of multiplexers includes exit multiplexers associated with a loop exit path and non-exit multiplexers. The computer-implemented method also includes traversing a topological order of the DFG in reverse. The computer-implemented method also includes computing fanin-cones for each two consecutive exit multiplexers. The computer-implemented method includes generating a truth table responsive to valid fanin-cones and back propagating select conditions for the each two consecutive exit multiplexers. The computer-implemented method includes eliminating an exit multiplexer from the each two consecutive exit multiplexers based on the truth table. The computer-implemented method further includes transforming the DFG to a new DFG based on the truth table.
    Type: Grant
    Filed: January 3, 2020
    Date of Patent: March 9, 2021
    Assignee: XILINX, INC.
    Inventors: Sumanta Datta, Aman Gayasen
  • Patent number: 10943043
    Abstract: Examples described herein provide a method for optimizing a netlist for an integrated circuit device. The method generally includes receiving a netlist comprising a first lookup table, and upstream logic, wherein the upstream logic receives a plurality of input signals and comprises at least one output connected as at least one input to the first lookup table, wherein the first lookup table comprises an unused input and multiple outputs; mapping the plurality of input signals directly to the at least one input and the unused input of the first lookup table; validating the mapping by monitoring the multiple outputs of the first lookup table; and upon a successful validation, optimizing the netlist by removing the upstream logic and reconnecting the plurality of input signals to the at least one input and the unused input of the first lookup table.
    Type: Grant
    Filed: March 26, 2020
    Date of Patent: March 9, 2021
    Assignee: XILINX, INC.
    Inventors: Jichun Wang, Chun Zhang, Fan Zhang, Bing Tian
  • Patent number: 10936941
    Abstract: The technical disclosure relates to artificial neural network. In particular, the technical disclosure relates to how to implement efficient data access control in the neural network hardware acceleration system. Specifically, it proposes an overall design of a device that can process data receiving, bit-width transformation and data storing. By employing the technical disclosure, neural network hardware acceleration system can avoid the data access process becomes the bottleneck in neural network computation.
    Type: Grant
    Filed: December 26, 2016
    Date of Patent: March 2, 2021
    Assignee: XILINX, INC.
    Inventors: Yubin Li, Song Han, Yi Shan
  • Patent number: 10936486
    Abstract: Techniques for providing address interleave support in a programmable device are described. In an example, a programmable integrated circuit (IC) includes a processing system, programmable logic, a plurality of master circuits disposed in the processing system, the programmable logic, or both the processing system and the programmable logic, an address interleave and transaction chopping circuit, a memory having a plurality of channels, and a system interconnect configured to couple the address interleave and transaction chopping circuit to the memory. The address interleave and transaction chopping circuit is configured to interleave memory transactions from the plurality of master circuits across the plurality of channels of the memory at a selected boundary.
    Type: Grant
    Filed: February 21, 2019
    Date of Patent: March 2, 2021
    Assignee: XILINX, INC.
    Inventor: Ian A. Swarbrick
  • Patent number: 10936311
    Abstract: Disclosed approaches for multiplying a sparse matrix by dense a vector or matrix include first memory banks for storage of column indices, second memory banks for storage of row indices, and third memory banks for storage of non-zero values of a sparse matrix. A pairing circuit distributes an input stream of vector elements across first first-in-first-out (FIFO) buffers according to the buffered column indices. Multiplication circuitry multiplies vector elements output from the first FIFO buffers by corresponding ones of the non-zero values from the third memory banks, and stores products in second FIFO buffers. Row-aligner circuitry organize the products output from the second FIFO buffers into third FIFO buffers according to row indices in the second memory banks. Accumulation circuitry accumulates respective totals from products output from the third FIFO buffers.
    Type: Grant
    Filed: July 9, 2019
    Date of Patent: March 2, 2021
    Assignee: Xilinx, Inc.
    Inventors: Ling Liu, Yifei Zhou, Xiao Teng, Ashish Sirasao, Chuanhua Song, Aaron Ng
  • Patent number: 10929331
    Abstract: Examples described herein generally relate to a layered boundary interconnect in an integrated circuit (IC) and methods for operating such IC. In an example, an IC includes a programmable logic region, a plurality of input/output circuits, a plurality of hard block circuits, and a programmable native transmission network. The programmable native transmission network is connected to and between the plurality of input/output circuits and the plurality of hard block circuits. The plurality of hard block circuits is connected to and between the programmable native transmission network and the programmable logic region.
    Type: Grant
    Filed: April 18, 2019
    Date of Patent: February 23, 2021
    Assignee: XILINX, INC.
    Inventor: Rafael C. Camarota
  • Patent number: 10930611
    Abstract: An integrated circuit assembly having an improved solder connection, and methods for fabricating the same are provided that utilize platelets within the solder connections to inhibit solder connection failure, thus providing a more robust solder interface. In one example, an integrated circuit assembly is provided that includes a package substrate having a first plurality of contact pads exposed on a first surface of the package substrate and a second plurality of contact pads exposed on a second surface of the package substrate. The second plurality of contact pads have a pitch that is greater than a pitch of the first plurality of contact pads. Interconnect circuitry is disposed in the package substrate and couples the first and second pluralities of contact pads. At least a first contact pad of the second plurality of contact pads includes a solder ball disposed directly in contact with a palladium layer.
    Type: Grant
    Filed: July 26, 2019
    Date of Patent: February 23, 2021
    Assignee: XILINX, INC.
    Inventors: Jaspreet Singh Gandhi, Tien-Yu Lee
  • Patent number: 10922463
    Abstract: Automated system design for a programmable integrated circuit (IC) includes conducting, using computer hardware, a dialogue with a user, wherein the dialogue describes a user design for the programmable IC, extracting, using the computer hardware, a first plurality of features for the user design from the dialog, and generating, using the computer hardware, a design specification for the user design based on the first plurality of features. Using the computer hardware, a device configuration for the user design is generated based on the design specification. The device configuration is loadable within the programmable IC to implement the user design.
    Type: Grant
    Filed: October 20, 2019
    Date of Patent: February 16, 2021
    Assignee: Xilinx, Inc.
    Inventors: Akhilesh Mahajan, K. Nithin Kumar, Yashwant Dagar
  • Patent number: 10924483
    Abstract: Roughly described, a network interface device receiving data packets from a computing device for transmission onto a network, the data packets having a certain characteristic, transmits the packet only if the sending queue has authority to send packets having that characteristic. The data packet characteristics can include transport protocol number, source and destination port numbers, source and destination IP addresses, for example. Authorizations can be programmed into the NIC by a kernel routine upon establishment of the transmit queue, based on the privilege level of the process for which the queue is being established. In this way, a user process can use an untrusted user-level protocol stack to initiate data transmission onto the network, while the NIC protects the remainder of the system or network from certain kinds of compromise.
    Type: Grant
    Filed: February 5, 2018
    Date of Patent: February 16, 2021
    Assignee: Xilinx, Inc.
    Inventors: Steven Leslie Pope, David James Riddoch, Ching Yu, Derek Edward Roberts
  • Patent number: 10924096
    Abstract: Apparatus and associated methods relate to a dynamic lane-to-lane skew reduction technique having (a) a clocking architecture configured to provide a corresponding first delayed clock signal and a corresponding second delayed clock signal through a first and a second plurality of routing traces, respectively, and (b) a number of skew compensation circuits configured to process the corresponding first delayed clock signal and the corresponding second delayed clock signal to generate a corresponding user clock signal for a corresponding lane of a transmitter. In an illustrative example, a first routing trace may transmit a first delayed clock signal in a direction opposite to a second routing trace transmitting a second delayed clock signal. By implementing the technique, each transmitter lane may receive a corresponding user clock signal having substantially the same delay relative to a reference clock signal such that dynamic lane-to-lane skew may be advantageously reduced.
    Type: Grant
    Filed: March 3, 2020
    Date of Patent: February 16, 2021
    Assignee: XILINX, INC.
    Inventors: Gourav Modi, Chee Chong Chan, Azarudin Abdulla, Riyas Noorudeen Remla
  • Patent number: 10922068
    Abstract: Updating firmware in an programmable integrated circuit (IC) includes determining, using a processor of a computer, a base address register (BAR) of an accelerator card from a device data file, wherein the accelerator card includes a programmable IC and is connected to the computer via a communication bus, mapping, using the processor, a feature PROM and a flash programmer circuit of the programmable IC to local memory of the computer using the BAR, and reading, over the communication bus, the feature PROM on the programmable IC to determine a programming mode for programming an external flash memory coupled to the flash programmer circuit. Based on the programming mode and using the processor, firmware is provided to the flash programmer circuit on the programmable IC via the communication bus. The flash programmer circuit is configured to program the firmware into the external flash memory.
    Type: Grant
    Filed: November 9, 2018
    Date of Patent: February 16, 2021
    Assignee: Xilinx, Inc.
    Inventors: Ryan F. Radjabi, Hem C. Neema, Sonal Santan, Yenpang Lin
  • Patent number: 10922226
    Abstract: An example computing system includes a memory, a peripheral device configured to send a page request for accessing the memory, the page request indicating whether the page request is for regular memory or scratchpad memory, and a processor having a memory management unit (MMU). The MMU is configured to receive the page request and prevent memory pages from being marked dirty in response to the page request indicating scratchpad memory.
    Type: Grant
    Filed: December 3, 2018
    Date of Patent: February 16, 2021
    Assignee: XILINX, INC.
    Inventors: Jaideep Dastidar, Chetan Loke
  • Patent number: 10924430
    Abstract: A system includes a host system and an integrated circuit coupled to the host system through a communication interface. The integrated circuit is configured for hardware acceleration. The integrated circuit includes a direct memory access circuit coupled to the communication interface, a kernel circuit, and a stream traffic manager circuit coupled to the direct memory access circuit and the kernel circuit. The stream traffic manager circuit is configured to control data streams exchanged between the host system and the kernel circuit.
    Type: Grant
    Filed: November 9, 2018
    Date of Patent: February 16, 2021
    Assignee: Xilinx, Inc.
    Inventors: Chandrasekhar S. Thyamagondlu, Hem C. Neema, Kenneth K. Chan, Ravi N. Kurlagunda, Karen Xie, Sonal Santan, Lizhi Hou