Patents Assigned to Xilinx, Inc.
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Patent number: 12212337Abstract: An integrated circuit (IC) device includes an error correction code (ECC) encoder circuitry configured to receive input data, determine min-terms in a Hamming matrix (H-Matrix) corresponding to the input data, and generate ECC data based on the min-terms and an output codeword based on the ECC data, and an error correction circuitry configured to generate a corrected output codeword based on the output codeword.Type: GrantFiled: March 30, 2023Date of Patent: January 28, 2025Assignees: XILINX, INC., Advanced Micro Devices, Inc.Inventors: Kumar Rahul, John J. Wuu, Santosh Yachareni
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Patent number: 12204940Abstract: Remote kernel execution in a heterogeneous computing system can include executing, using a device processor of a device communicatively linked to a host processor, a device runtime and receiving from the host processor within a hardware submission queue of the device, a command. The command requests execution of a software kernel and specifies a descriptor stored in a region of a memory of the device shared with the host processor. In response to receiving the command, the device runtime, as executed by the device processor, invokes a runner program associated with the software kernel. The runner program can map a physical address of the descriptor to a virtual memory address corresponding to the descriptor that is usable by the software kernel. The runner program can execute the software kernel. The software kernel can access data specified by the descriptor using the virtual memory address as provided by the runner program.Type: GrantFiled: January 17, 2022Date of Patent: January 21, 2025Assignee: Xilinx, Inc.Inventors: Sonal Santan, Yu Liu, Yenpang Lin, Stephen P. Rozum
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Patent number: 12200087Abstract: A computing node for a computing system includes a processor, conversion circuitry, and routing circuitry. The processor generates a data signal based on a function of an application executed by the computing system. The data signal has a first precision format and a first sparse representation. The conversion circuitry receives the data signal from the processor and generate a converted data signal by at least one of converting the first precision format to a second precision format and converting the first sparse representation to a second sparse representation. The routing circuitry transmits the converted data signal to switch circuitry of the computing system.Type: GrantFiled: December 13, 2022Date of Patent: January 14, 2025Assignee: XILINX, INC.Inventors: Edward Richter, Paul Hartke, Philip James-Roxby
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Patent number: 12190077Abstract: A communication system includes link circuits that receive serial data over one or more input serial links. The link circuits include a primary link circuit and a secondary link circuit. The secondary link circuit includes a de-serializer circuit configured to receive the serial data from the one or more input serial links and convert the serial data into parallel data, and an aligner circuit comprising a memory. The aligner circuit stops at least one of storing the parallel data in the memory and reading the memory based on a channel bonding signal generated based on a channel bonding symbol within the serial data. The aligner circuit outputs the channel bonding signal to a finite state machine (FSM) circuit of the primary link circuit. The aligner circuit outputs the parallel data based on receiving a read signal from the FSM circuit of the primary link circuit.Type: GrantFiled: November 23, 2022Date of Patent: January 7, 2025Assignee: XILINX, INC.Inventors: Sai Ram Venkata Pattabhi Nedunuri, Killivalavan Kaliyamoorthy
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Patent number: 12191876Abstract: Methods and apparatus for calibrating a gain for a circuit block are disclosed. An example method includes receiving a plurality of quantizer offsets, where the plurality of quantizer offsets represent calibration data for a quantizer configured to quantize an output of the circuit block, determining one or more differences based on one or more first quantizer offsets of the plurality of quantizer offsets and on one or more second quantizer offsets of the plurality of quantizer offsets, and determining an incremental change in a gain associated with the circuit block based on the one or more differences.Type: GrantFiled: December 27, 2022Date of Patent: January 7, 2025Assignee: Xilinx, Inc.Inventors: Bob Verbruggen, Christophe Erdmann
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Patent number: 12190994Abstract: An integrated circuitry (IC) device for a memory device includes driver circuitry, selection circuitry, clock generation circuitry, and self-time path circuitry. The driver circuitry generates a plurality of driver circuitry outputs. The selection circuitry selects one of the plurality of driver circuitry outputs based on a plurality of enable signals. The clock generation circuitry receives the selected one of the plurality of driver circuitry outputs from the selection circuitry, and generates a clock signal based on at least the selected one of the plurality of driver circuitry outputs from the selection circuitry. The self-time path circuitry of a memory receives the clock signal and generates a reset signal based on the clock signal. The plurality of driver circuitry outputs and the clock signal are based on the reset signal, and the self-time path circuitry corresponds to one or more columns of a memory bank.Type: GrantFiled: December 29, 2022Date of Patent: January 7, 2025Assignee: XILINX, INC.Inventors: Kumar Rahul, Santosh Yachareni, Mahendrakumar Gunasekaran, Mohammad Anees
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Publication number: 20250004983Abstract: Examples herein describe a three-dimensional (3D) die stack. The 3D die stack includes a programmable logic (PL) die and a compute die stacked on top of the PL die. The PL die includes a plurality of configurable blocks and a plurality of first electrical connections on a top side of the PL die. The compute die includes a plurality of data processing engines and a plurality of second electrical connections on a bottom side of the compute die. The three-dimensional die stack includes a plurality of tiles, each tile comprising M configurable blocks included in the plurality of configurable blocks and N data processing engines included in the plurality of data processing engines.Type: ApplicationFiled: June 28, 2023Publication date: January 2, 2025Applicant: XILINX, INC.Inventors: Brian C. GAIDE, Sneha Bhalchandra DATE, Juan J. NOGUERA SERRA
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Publication number: 20250004961Abstract: A direct memory access (DMA) system includes a read request circuit configured to receive read requests from a plurality of client circuits. The DMA system includes a response reassembly circuit configured to reorder read completion data received from a plurality of different hosts in response to the read requests. The DMA system includes a read scheduler circuit configured to schedule conveyance of the read completion data from the response reassembly circuit to the plurality of client circuits. The DMA system includes a data pipeline circuit implementing a plurality of data paths coupled to respective ones of the plurality of client circuits for conveying the read completion data as scheduled by the read scheduler circuit.Type: ApplicationFiled: June 29, 2023Publication date: January 2, 2025Applicant: Xilinx, Inc.Inventors: Chandrasekhar S. Thyamagondlu, Kushagra Sharma, Surender Reddy Kisanagar
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Publication number: 20250004919Abstract: An integrated circuit includes a compute circuit and a trace data mover circuit coupled to the compute circuit. The trace data mover circuit is configured to convey trace data generated by the compute circuit to a destination circuit. The trace data mover circuit includes a controller circuit configured to receive a stream of trace data from the compute circuit and generate instructions for writing the trace data. The trace data mover circuit includes a writer circuit configured to write the trace data to the destination circuit responsive to the instructions generated by the controller circuit.Type: ApplicationFiled: June 27, 2023Publication date: January 2, 2025Applicant: Xilinx, Inc.Inventors: Anurag Dubey, Paul Robert Schumacher
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Publication number: 20250004941Abstract: A computer-implemented method for memory management can include identifying a set of one or more memory blocks of virtual memory to be allocated for storage of a content into a plurality of memory banks that subdivide physical memory. The method can include storing the content in the set of one or more memory blocks of virtual memory. The method can include assigning an identifier to the set of one or more memory blocks of virtual memory that store the content. The method can include outputting the identifier for the set of one or more memory blocks of virtual memory. Various other methods, systems, and computer-readable media are also disclosed.Type: ApplicationFiled: June 30, 2023Publication date: January 2, 2025Applicant: Xilinx, Inc.Inventors: Duncan Andrew Cockburn, David James Fraser, Inaki Ormaetxea, Gareth David Edwards, Dmitri Kitariev, David Riddoch, Victor Wu
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Publication number: 20250005246Abstract: Compiling a tensor specification for multi-dimensional direct memory access circuit configurations includes generating a first list of tile combination objects from a tensor tiling specification. The first list specifies a sequence of tiles specified by the tensor tiling specification in which each tile object represents a single tile of a tensor data structure. A second list of tile combination objects is generated by combining selected ones of the tile combination objects from the first list. Each tile combination object of the second list represents one or more tile objects. The tile combination objects of the second list are converted into buffer descriptor objects that include buffer descriptor parameters. Each of the buffer descriptor objects that is non-compliant with hardware constraints corresponding to a data mover circuit that is configurable using the buffer descriptor objects is legalized. The buffer descriptor objects are output, as legalized.Type: ApplicationFiled: June 30, 2023Publication date: January 2, 2025Applicant: Xilinx, Inc.Inventors: Chia-Jui Hsu, Fnu Sindhoori
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Publication number: 20250004782Abstract: A computer-implemented method for managing processing order for a plurality of commands can include in response to receiving each command of a plurality of commands in a receipt order, assigning each respective command of the plurality of commands to a respective processing queue of a plurality of processing queues to be processed, and setting, for each of the plurality of commands and in the receipt order, an identifier based on the respective queue assigned to each of the plurality of commands, and managing, based on the identifiers for each of the plurality of commands in the receipt order, an order of processing of each of the plurality of commands from the respective processing queue of the plurality of processing queues. Various other methods, systems, and computer-readable media are also disclosed.Type: ApplicationFiled: June 30, 2023Publication date: January 2, 2025Applicant: Xilinx, Inc.Inventors: Mark Richard Nethercot, Martin Rhodes, Ricardo Gonzalez Toral, Colin Stirling, Dmitri Kitariev, David Riddoch
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Publication number: 20250005249Abstract: Reducing power consumption of a circuit design includes, for a circuit block of a circuit design, where the circuit block has a plurality of signals, selecting one or more signals of the plurality of signals. Prediction and gating circuitry are generated. The prediction and gating circuitry include a predictor circuit configured to generate a prediction of an output of the circuit block based on the one or more signals as selected and gate the circuit block based on the prediction of the output of the circuit block. The prediction and gating circuitry include an output circuit configured to substitute a constant value as the output of the circuit block responsive to gating the circuit block by the predictor circuit. The prediction and gating circuitry are inserted within the circuit design.Type: ApplicationFiled: June 29, 2023Publication date: January 2, 2025Applicant: Xilinx, Inc.Inventors: Fan Zhang, Chaithanya Dudha, Nithin Kumar Guggilla
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Publication number: 20250007684Abstract: A computer-implemented method for managing channel accessibility can include detecting, by a first circuit, a transmit request from the first circuit to transmit a message into a communication channel connecting the first circuit to second circuit. The method can include determining, by the first circuit, whether to approve the transmit request based on an evaluation of a first number associated with messages previously transmitted by the first circuit to the second circuit over the communication channel and a second number associated with processing by the second circuit of the messages previously transmitted by the first circuit. The method can include, in response to determining to approve the transmit request, transmitting, by the first circuit, the message into the communication channel. Various other methods, systems, and computer-readable media are also disclosed.Type: ApplicationFiled: June 30, 2023Publication date: January 2, 2025Applicant: Xilinx, Inc.Inventors: Mark Richard Nethercot, Martin Rhodes, David Riddoch, Connor Hughes, Gareth David Edwards
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Patent number: 12183311Abstract: A clock buffer has a clock-in port that inputs a reference clock and an enable port that inputs a video-clock-enable signal from a video receiver. The clock buffer generates a video pixel clock signal that has pulses of the reference signal as enabled by the video-clock-enable signal. The video receiver includes a link symbol extractor, a link-to-pixel mapper, and a timing generator that work to mirror the actual pixel data rate from the active period in a blanking period and thereby recover the actual video pixel clock.Type: GrantFiled: November 2, 2022Date of Patent: December 31, 2024Assignee: XILINX, INC.Inventors: Killivalavan Kaliyamoorthy, Nedunuri Venkata Pattabhi Sai Ram, Phani Krishna Kondepudi, Kapil Usgaonkar, Pankaj Vasant Kumbhare
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Patent number: 12182552Abstract: A computer-based technique for processing an application includes determining that a loop of the application includes a reference to a data item of a vector data type. A trip count of the loop is determined to have an unknown trip count. The loop is split into a first loop and a second loop based on a splitting factor. The second loop is unrolled.Type: GrantFiled: May 24, 2022Date of Patent: December 31, 2024Assignee: Xilinx, Inc.Inventor: Ajit K. Agarwal
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Patent number: 12176900Abstract: An electronic system includes a buffer and analog-to-digital circuitry. The buffer includes buffer circuitry that includes an input node that receives an input signal. The buffer circuitry further includes coil circuitry that is electrically connected to the input node and a first node. The coil circuitry includes a first inductor and a second inductor. Further, the buffer circuitry includes a resistor that is electrically connected to the first node and a second node. A capacitor of the buffer circuitry is electrically connected to the second node and a third node. The third node is disposed between the first inductor and the second inductor. The buffer circuitry is configured to output an output signal based on the input signal.Type: GrantFiled: August 9, 2022Date of Patent: December 24, 2024Assignee: XILINX, INC.Inventor: Roswald Francis
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Patent number: 12176896Abstract: An integrated circuit (IC) may include a plurality of compute tiles in a data processing array. Each compute tile is configured to perform a data processing function. The IC may include a plurality of interface tiles in the data processing array. The plurality of interface tiles are communicatively linked to the plurality of compute tiles. The IC may include a plurality of programmable stream switches disposed in the plurality of compute tiles and the plurality of interface tiles. The IC may include a functional safety circuit. The functional safety circuit is connected to a selected programmable stream switch of the plurality of programmable stream switches. The functional safety circuit is configured to perform a functional safety function on a plurality of data streams routed to the functional safety circuit from the selected programmable stream switch.Type: GrantFiled: December 7, 2022Date of Patent: December 24, 2024Assignee: Xilinx, Inc.Inventor: Karl Henrik Goran Bilski
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Patent number: 12175622Abstract: A smart cache implementation for image warping is provided by dividing an output image into a plurality of blocks corresponding to initial coordinates in the output image; dividing an input image into at least a first and second regions of pixels, where the first region overlaps the second region; generating an unsorted remap vector of the plurality of blocks for image warping the input image; identifying a first and second subsets of blocks from the plurality of blocks that can be reconstructed using the first and second regions respectively; generating a region-based sorting, a line-based sorting of the region-based sorting, a column-based sorting of the line-based sorting based on the initial x-coordinates of the blocks in the unsorted remap vector, and a sorted remap vector by sorting the column-based sorting based on initial y-coordinates of the blocks in the unsorted remap vector.Type: GrantFiled: March 12, 2021Date of Patent: December 24, 2024Assignee: XILINX, INC.Inventors: Sandip Kothari, Vivek Veenam, Adhipathi Reddy Aleti, Jagadeesh Banisetti
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Publication number: 20240419878Abstract: A method, system, and circuit arrangement involve synthesizing a circuit design specified in a register transfer level (RTL) specification into a netlist. The RTL specification includes an assert statement that specifies a conditional expression involving one or more signals specified in the circuit design to be checked during simulation, and the synthesizing includes synthesizing the assert statement into netlist elements. The design tool places and routes the netlist into a circuit design layout and generates implementation data from the layout.Type: ApplicationFiled: June 19, 2023Publication date: December 19, 2024Applicant: Xilinx, Inc.Inventors: Anil Kumar A V, Alok Mistry