Abstract: In one embodiment, a method of generating a circuit design is provided. For each data terminal connecting a plurality of components in a circuit design, a respective list of dimensions of data used by the data terminal are determined. A plurality of exchange orderings are generated that each indicate an order in which dimensions are exchanged between the lists. For each exchange ordering, dimensions are exchanged between the lists according to the exchange ordering to produce a set of supplemented lists of dimensions. A set of buffers for buffering data between the data terminals are determined based on the supplemented lists of dimensions. Memory requirements are determined for each of the set of buffers. The circuit design is modified to include the one of the determined sets of buffers having a lowest memory requirement.

Abstract: A capacitor in an integrated circuit (“IC”) has a distribution grid formed in a first patterned metal layer of the integrated circuit and a first vertical conductive filament connected to and extending away from the distribution grid along a first direction. A second vertical conductive filament is connected to the distribution grid and extends in the opposite direction. First and second grid plates are formed in the metal layers above and below the first patterned metal layer. The grid plates surround the first and second vertical conductive filaments. The distribution grid, first vertical conductive filament and second vertical conductive filament are connected to and form a portion of a first node of the capacitor and the first grid plate and the second grid plate are connected to and form a portion of a second node of the capacitor.

Abstract: An inductor for an integrated circuit can include a first turn comprising a first through silicon via (TSV) coupled to a second TSV. The inductor can include a third TSV coupled to the second TSV.

Abstract: An integrated circuit enabling the communication of data is described. The integrated circuit comprises an input/output port; a plurality of data converter circuits; and programmable interconnect circuits coupled between the input/output port and the plurality of data converter circuits, the programmable interconnect circuits enabling a connection of the plurality of data converter circuits to the input/output port of the integrated circuit. A method of enabling the communication of data in an integrated circuit is also described.

Abstract: A symmetrical inductor includes an integrated circuit having a plurality of conductive layers. A first loop is disposed in an upper layer of the conductive layers, and at least two strapped loops are disposed in at least two layers of the conductive layers, respectively. The strapped loops are coupled in series to the first loop, and the at least two layers are below the upper layer. A second loop is disposed in the upper layer and is coupled in series to the at least two strapped loops. A first terminal electrode is coupled to the first loop, and a second terminal electrode is coupled to the second loop. A center-tap electrode is coupled to the at least two strapped loops.

Abstract: A circuit controls a memory arrangement and includes an array of programmable resources and interconnect resources, a reconfiguration port, and a processor. The programmable resources and interconnect resources in the array are initially configured with a reference configuration data-set. The reference configuration data-set configures the programmable resources and interconnect resources to implement a general memory controller. The processor obtains a characteristic of the memory arrangement and selects a particular partial reconfiguration data-set based on the characteristic of the memory arrangement. The processor reconfigures the programmable resources and interconnect resources in the array via the reconfiguration port. The processor reconfigures the programmable resources and interconnect resources with the particular partial reconfiguration data-set.

Abstract: In one embodiment of the invention, a voltage-mode line driver circuit is provided for transmitting a differential signal. The voltage-mode line driver includes a first voltage swing circuit having an input coupled to receive an input signal and an output coupled to a first transmission line. A second voltage swing circuit is included, the second voltage swing circuit having an input coupled to receive an inversion of the input signal and an output coupled to a second transmission line. First and second pre-emphasis circuits are respectively coupled to the first and second voltage swing circuits. The first and second pre-emphasis circuits are configured to supplement the slew rate of respective first and second voltage swing circuits in response to a transition of the input signal.

Abstract: A method and system of detecting data imprinting in a memory is described. Data having known bit values is stored in a location in the memory and the data is read to determine the amount of the known bit values that can be successfully read after an attempt to erase the data. The amount of data that can be successfully read is compare to a threshold. Data bit values of a payload data are inverted to reverse the effects of data imprinting in response to the determined amount exceeding the threshold.

Abstract: A method or system for generating a packet processor inputs a first specification describing the packet processor, generates a parsing tree and generates a second specification describing a programmable compute pipeline. The parsing tree is generated from the actions of the first specification. The parsing tree has multiple levels and each level specifies one or more concurrent sets of elementary operations. The parsing tree also specifies for each level a respective bound on the elementary operations in the concurrent sets of the level. The programmable compute pipeline includes multiple stages for implementing the actions. Each stage corresponds to one of the levels of the parsing tree and includes one or more elementary components, with a number of the elementary components equaling or exceeding the respective bound for the level. The elementary components in the stage are programmable to concurrently perform combinations that include each concurrent set for the level.

Abstract: A method is provided for generation of a circuit design. A plurality of components, including at least a processor and a peripheral device, is instantiated in a circuit design. One or more parameterizable data bus interface blocks are automatically selected based on the master-slave relationships, requirements, and capabilities of the components. The one or more parameterizable data bus interface blocks are instantiated in the circuit design. In response to user input, values are assigned to one or more parameters of the processor. The plurality of components and data bus interface blocks are automatically parameterized by determining appropriate parameter values according to the parameters of the processor and capabilities and requirements of the components and data bus interface blocks.

Abstract: An integrated circuit can include an input/output (I/O) bank. The I/O bank can include a plurality of byte clock groups. Each byte clock group can include at least one phaser configured to clock circuit elements of the byte clock group at a frequency at which a source synchronous device coupled to the byte clock group communicates data.

Abstract: A programmable integrated circuit is disclosed. The programmable integrated circuit comprises a matrix of circuit blocks, each circuit block of the matrix of circuit blocks comprising configurable blocks; and a routing network coupled to the matrix of circuit blocks, the routing network having a plurality of programmable interconnect points comprising buffers enabling asynchronous communication. A method of asynchronously routing data in an integrated circuit is also disclosed.

Abstract: In one embodiment, a device is disclosed. For example, in one embodiment of the present invention, the device comprises a first memory stage for storing a plurality of pointer values associated with a plurality of buffers, wherein the plurality of buffers is associated with a plurality of logical channels. The device further comprise a second memory stage, wherein an access address to the second memory stage is formed from a concatenation of one of the plurality of pointer values and a channel number corresponding to one of the plurality of logical channels.

Abstract: An embodiment of a method for enabling a high level modeling system for implementing a circuit design in an integrated circuit device includes: receiving a high-level characterization of the circuit design; receiving a portable location constraint associated with elements of the circuit design; and generating, by a computer, a low-level characterization of the circuit design based upon the high-level characterization and the portable location constraint.

Abstract: A multi-port memory controller (MPMC) can be parameterized to selectively connect to different memory configurations. In particular, a programmable device that is combined with a DRAM in a die-stacked distributed memory in a single chip is provided with the programmable device forming the MPMC. The programmable device is parameterized to form a memory controller that can either aggregate or segment memory controller components to control different DRAM memory banks either together or separately. The aggregation or segmentation of the memory devices can be configured dynamically during operation of the programmable device.

Abstract: A security circuit for a reprogrammable logic IC includes an evolved circuit that ties the performance of the security circuit to the physical properties of that particular reprogrammable logic IC. The security circuit can be a decryption and/or encryption circuit that decrypts and/or encrypts, respectively, a configuration bitstream for the IC. Because of the link between the performance of the security circuit and the physical properties of the IC, the security circuit cannot be used in other ICs. For example, an encrypted bitstream that can be decrypted by the security circuit in a first IC will typically not be decrypted by the same security circuit in a second IC, since the physical properties of the two ICs will typically be different. The evolved circuit can comprise a portion of the security circuit, such as a security key generator, or it can comprise the full security circuit.

Abstract: A technique for setting Vgg in an IC is disclosed. The technique includes specifying a design reliability lifetime for the IC, and a relationship between maximum gate bias and gate dielectric thickness for the IC sufficient to achieve the design reliability lifetime is established. The IC is fabricated and the gate dielectric thickness is measured. A maximum gate bias voltage is determined according to the gate dielectric thickness and the relationship between maximum gate bias and gate dielectric thickness, and a Vgg trim circuit of the IC is set to provide Vgg having the maximum gate bias voltage that will achieve the design reliability lifetime according to the measured gate dielectric thickness.

Abstract: An embodiment of the invention pertains to demodulating a data communication into a sequence of symbols. In this embodiment, a first filter generates a first convolution between a first plurality of coefficients and the data communication. The data communication is a distortion of a first sequence of symbols selected from a plurality of symbols in a constellation. A first error circuit maps the first convolution to a second sequence of symbols. An adaption circuit adjusts the first coefficients until a convergence at a last one of the symbols in the second sequence. A second filter generates a second convolution between a second plurality of coefficients and the data communication. The second coefficients are initialized to the first coefficients from the adaption circuit. A second error circuit maps the second convolution to a third sequence of symbols.

Abstract: An apparatus for interconnecting a first die and a second die of a multi-die device includes a master circuit block that interfaces with the first die of the multi-die device, a slave circuit block that interfaces with the second die of the multi-die device, a first memory in the slave circuit block, a second memory in the master circuit block, and a plurality of ?bumps between the first die and the second die, wherein the master circuit block and the slave circuit block are configured to identify one of the ?bumps as a faulty ?bump, and store a first value that corresponds with the identified faulty ?bump in the first memory.

Abstract: A direct digital synthesis is provided with added circuitry to reduce jitter in an IC so that a programmable frequency output can be provided near the limits of the IC system clock with minimal jitter. The system derives the quotient Q as a remainder R in an accumulator at the instant of an overflow, divided by a programmable input N. The quotient Q is subjected to conversion logic that can be provided by a fast parallel to serial converter such as, for example a multi-gigabit transceiver (MGT) of an FPGA. As an alternative to an MGT, a series of delay devices such as found in a carry chain can be used if calibration is performed to assure the accuracy of delays.