Abstract: A method of minimizing power consumption in an integrated device is disclosed. The method comprises providing a plurality of circuit blocks having circuits for performing logic functions, wherein each circuit block consumes power in a static state; coupling one of a plurality of operating voltages to each circuit block of the plurality of circuit blocks; enabling a reduction of power consumed by a first set of circuit blocks by way of a first power reduction signal; and enabling a reduction of power consumed by a second set of circuit blocks by way of a second power reduction signal. A circuit for minimizing power consumption in a device is also disclosed.

Abstract: A circuit for determining a process corner for a CMOS device of an integrated circuit is disclosed. The circuit comprises a CMOS monitoring circuit comprising an NMOS transistor and a PMOS transistor of the integrated circuit; reference circuit comprising elements for generating a reference voltage for an NMOS transistor and a reference voltage for a PMOS transistor; a first comparator for comparing a voltage generated by the NMOS transistor monitored by the CMOS monitoring circuit with the reference voltage for a NMOS transistor; and a second comparator for comparing a voltage generated by the PMOS transistor monitored by the CMOS monitoring circuit with the reference voltage for a PMOS transistor. A method for determining a process corner for CMOS devices of an integrated circuit is also disclosed.

Abstract: A method of evaluating an architecture for an integrated circuit device is disclosed. The method comprises generating a library of primitives for a predetermined architecture; transforming an original dataflow program into an intermediate format; transforming the intermediate format to a dataflow program defined in terms of the predefined library of primitives; and generating an implementation profile comprising information related to an implementation of the original dataflow program in an integrated circuit having the predetermined architecture. A method of evaluating an architecture for an integrated circuit device is also disclosed.

Abstract: Generating a pipeline for processing a type of network packets. A specification is input of the processing of the type of network packets. The specification specifies actions for inspecting and modifying one or more of the fields of the type of network packets. Assignments are generated that assign each of the actions to a corresponding stage of the pipeline. One or more of the actions is assigned to each stage of the pipeline. One or more quality metrics is evaluated for each of the assignments. A specific one of the assignments is selected in response to the quality metric or quality metrics. The pipeline is generated for the specific assignment. Each stage of the pipeline implements each action assigned to the stage.

Abstract: A computer-implemented method of predicting a clock period within an integrated circuit can include determining configuration information for the integrated circuit (1430, 1435, 1445) and determining at least one measure of directional shift for an edge of a pulse of a reference clock signal of the integrated circuit with reference to at least one other clock signal of the integrated circuit (1440, 1450, 1460). The measure of directional shift for the edge of the pulse of the reference clock signal can be output (1475).

Abstract: Method and apparatus for profiling a hardware/software embedded system are described. In one example, a hardware co-simulation interface is generated between a programmable logic device (PLD) configured with the embedded system and a computer based on a plurality of events. The embedded system in the PLD is simulated. During the simulation of the embedded system, occurrence of at least one event is detected to produce profiling data. The profiling data is stored into shared first-in-first-out (FIFO) logic of the PLD and the computer. The profiling data is retrieved from the shared FIFO logic at the computer.

Abstract: A computer-implemented method of implementing a circuit design within a programmable logic device can include selecting at least one circuit element of the circuit design. The selected circuit element can be converted to a latch. A timing analysis can be performed upon the circuit design after conversion of the selected circuit element to a latch. A determination can be made by a computer as to whether the timing of the circuit design improves and the conversion of the selected circuit element to a latch can be accepted when the timing of the circuit design improves. The circuit design can be output.

Abstract: A computer-implemented method of incorporating a module within a circuit design can include, responsive to identifying the module to be imported into the circuit design, automatically identifying each port of the module, displaying a list of the ports of the module, and receiving a user input selecting a plurality of ports of the module for inclusion in an interface through which the module communicates with the circuit design. Responsive to a user input specifying an interface type, the interface type can be associated with the plurality of ports. The interface type can be associated with a port list including standardized ports. Individual ones of the plurality of ports can be automatically matched with standardized ports from the port list. A programmatic interface description specifying the interface for the module can be output.

Abstract: Approaches for estimating power consumption of a circuit from a circuit design. According to one embodiment, a representation of the circuit design specifies a plurality of circuit elements for implementing the circuit design. The circuit elements are matched to structural templates. Each structural template is representative of one or more circuit elements and has associated information descriptive of one or more toggle rates. Respective estimated toggle rates are determined for the circuit elements of the circuit design based on the information descriptive of one or more toggle rates associated with the matched structural templates. An estimated power consumption level is determined as a function of the estimated toggle rates of the circuit elements, and data indicative of the estimated power consumption level is output.

Abstract: A fuse structure for a semiconductor integrated circuit (IC) can include a first node comprising a region of a metal layer of an IC manufacturing process and a second node comprising a region of a conductive layer residing on a layer of the IC manufacturing process below the metal layer of the first node. The fuse structure can include a fuse link comprising a conductive material, positioned substantially perpendicular to each of the metal and conductive layers. An upper end of the fuse link couples to the first node and a lower end of the fuse link, that is distal to the upper end, couples to the second node.

Abstract: Approaches for preparing simulation models of an electronic circuit are disclosed. The design is partitioned into first and second clusters. The design includes a source module in the first cluster connected to a destination module in the second cluster. The first cluster is compiled into a first model for a software-based co-simulation platform for simulating behavior of the source module using the first model. The first cluster and the second cluster of the design are compiled into a second model for a hardware-based co-simulation platform that includes a programmable logic circuit configurable for emulating behavior of the design using the second model. An interconnection block is generated and stored in the second model. The interconnection block is switchable between coupling of the destination module in the second model to the source module of the first model or to a source module of the second model.

Abstract: The dual inductor structure can include a first inductor including a first plurality of coils. Each coil of the first plurality of coils can be disposed within a different one of a plurality of conductive layers. The coils of the first plurality of coils can be vertically stacked and concentric to a vertical axis. The dual inductor structure further can include a second inductor including a second plurality of coils. Each of the second plurality of coils can be disposed within a different one of the plurality of conductive layers. The coils of the second plurality of coils can be vertically stacked and concentric to the vertical axis. Within each conductive layer, a coil of the second plurality of coils can be disposed within an inner perimeter of a coil of the first plurality of coils.

Abstract: A design hierarchy based on an implementation set abstraction of a user design for an integrated circuit design includes a plurality of nodes and a definition for each of the nodes in the plurality of nodes that describes the type of elements contained in each node and the hierarchy defined by each of the nodes. Each node can include at least one implementation element of the design and the at least one implementation element can be selected among the group including a set of logical elements, a set of placed elements, and a set of placed and routed elements.

Abstract: A serializer is provided to serialize combined synchronization information and data blocks for transmission over the high-speed channel. A gearbox combines synchronization information with data blocks to present to the serializer. A scrambler scrambles data blocks to present to the gearbox. An encoding device stores a program that contains instructions to format the data blocks for sending over the high-speed channel. The formatting reduces a number of operations used to receive the data blocks by a receiver.

Abstract: A varactor circuit and voltage-controlled oscillation are described. The varactor circuit includes a first varactor, a second varactor, a third varactor, and a fourth varactor. A first source-drain node of the first varactor and a second source-drain node of the second varactor are coupled to a first input node. A first gate node for the first varactor is coupled to a first output node. A second gate node for the second varactor is coupled to a second output node. A third gate node for the third varactor and a fourth gate node for the fourth varactor are coupled to a second input node. A third source-drain node of the third varactor is coupled to the first output node. A fourth source-drain node of the fourth varactor is coupled to the second output node. In other embodiments, varactor circuits block and re-center VCO output CML.

Abstract: An input/output (“I/O”) circuit has a first N-channel metal-oxide semiconductor (“NMOS”) field-effect transistor (“FET”) coupled to the input pin with a silicide block. A first P-channel metal-oxide semiconductor (“PMOS”) FET is directly connected to the input pin, with its N-well electrically coupled to an ESD well bias circuit. An NMOS low-voltage differential signal (“LVDS”) driver is also directly connected to the input pin, and has cascaded NMOS FETs. The first NMOS FET of the LVDS driver is fabricated within a first P-tap guard ring electrically coupled to ground and an N-well guard ring coupled to the ESD well bias. The second NMOS FET of the LVDS driver is fabricated within a second P-tap guard ring electrically coupled to ground.

Abstract: A data storage system includes a first circuit board, a plurality of sockets coupled to the first circuit board, an connector coupled to each of the sockets for coupling each of the sockets to external circuitry, and a plurality of memory modules, each memory module disposed within one of the sockets. The memory module includes a circuit board, an integrated circuit device having configurable blocks, DRAM devices that form parallel channels of DRAM memory and flash memory devices that form parallel channels of flash memory. The memory module also includes an interface electrically coupled to the integrated circuit device for coupling input and output between the integrated circuit device and external circuitry.

Abstract: Circuit design fitting for an integrated circuit is described. A mapped design for the circuit design is obtained. A first placement of the mapped design in association with an integrated circuit is performed. Circuit blocks are marked associated with the integrated circuit with control set identifiers. A circuit object is associated with a control set identifier. A site for placement of the first circuit object is located. The site is associated with a circuit resource block, which is associated with circuit resource blocks of the integrated circuit. Nearest neighbor circuit resource blocks with respect to the circuit resource block are acquired. The nearest neighbor circuit resource blocks of the circuit resource block are categorized in response to statuses. The circuit object is placed in a nearest neighbor of the nearest neighbor circuit resource blocks of the circuit resource block for a second placement.

Abstract: A method of calibrating memory controller signals within an integrated circuit (IC) can include determining an internal delay of a clock network of the IC and generating a calibrated clock signal by applying a first delay to an uncalibrated clock signal, wherein the first delay is determined by subtracting the internal delay of the clock network of the IC from a bitperiod of the uncalibrated clock signal. The method can include determining a classification of at least one data signal according to timing of positive and negative edges of the at least one data signal in comparison with edges of the calibrated clock signal and aligning at least one of positive or negative edges of the at least one data signal to occur at midpoints between edges of the calibrated clock signal according to the classification of the at least one data signal.

Abstract: A multilevel shared database for routing for an integrated circuit is described. An aspect relates generally to a database comprising routing edges defined by tile templates. The routing edges are associated with a plurality of wire length segmentations. The tile templates are associated with tiles of an integrated circuit. The tiles are repeated circuit blocks forming an array. A portion of the tile templates are shared among a portion of the tiles such that the tile templates are less in number than the tiles. The tile templates are associated with pointers for pointing to wire templates.